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In the lower-end STM32L4, covered by RM0394, SRAM is partitioned into two parts, SRAM1 and SRAM2.SRAM2 (besides being "special" in that it has ECC and automatic erase facities), is mapped at both 0x1000'0000 and at the end of SRAM1 in the 0x200x'xxxx...
Hi, everyoneI recently encountered a strange phenomenon. I opened three DMA channels on the STM32G474RBT6.The first one is Channel 1 of DMA1 (circular mode), which is used for automatically collecting the data converted by ADC.The second one is chann...
Been reading thru the F103 datasheet to try and figure out why my TinyUSB based code isn't working. The datasheet says.. "For mono-directional/single-buffer endpoints, a single register can be used to implement two distinct endpoints". The F103 has...
Hello, We are facing an intermittent CAN-FD issue in the field and would appreciate guidance from the community. Our system has two devices on the bus (no other device on the bus) using a request–response architecture. The master sends a request ever...
I have a situation where a USB endpoint stops working due to a control packet being NAKed in the handshake phase. I've traced the problem down to the STM USB stack setting DCTL.SGONAK = 1 in response to an INCOMPISOOUT event, yet in the case when it ...
Hi everyone,I am using a STM32H563RG and I need the RTC to work even if the VDD is powered off. To do that, I am plugging a battery on the VBAT pin to power the RTC and the Backup domain. But I tested it and it seems the RTC is stopped and the backup...
Hello,I have not found the maximum TRACECLK frequency of the STM32H725 in the documentation. It looks like it is generated by PLL1 with flexible division ratios and thus can attain values that are not realistic for I/Os (100 to 220 MHz for Speed 11 a...
I am having a custom board having STM32N657I0H3Q interfaced with quad flash MX25R6435FM2IL0. I am unable to access (both read and write) to the flash MX25R6435FM2IL0.I have attached Saleae capture (configured the flash in single mode only for Saleae ...
Hello, I am reading 6.3.30 LCD-TFT controller (LTDC) section to interface with DS90C385A (LCD) or ADV7125 (VGA) Assume that LCD Clock (pixel clock) polarity is set to high. Ideally, we can expect rising edge of clock aligned to the middle of the data...
Hello, How to perform dual-core communication on STM32H747?
