STM32 MCUs Products

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Resolved! LPTIM current consumption

Hello, For my research work I want to characterize how much current the LPTIM of a STM32U575ZIT6Q consumes when in compare match mode (counting from 0 to 65535 repeatedly).I prorgrammed two very simple codes, one where the counter is not initialized ...

MCU current.jpeg
R.uy by Associate II
  • 1060 Views
  • 1 replies
  • 2 kudos

STM32F407VET6 FSMC to LCD driver

I want to try to interface a 7" 1024X600 display with the STM32F407VET6 chip. I know that the F407 does not have a LTDC so I was wondering if I could use a LCD driver chip that could be wired to the FSMC of the microcontroller. I also plan on using a...

I'm writing the following code: GPIOA-"MODER" 0x400; (set GPIO_MODER_MODE5_0). It's not working! In the debugging window, bit 11 doesn't change and the LD4 LED doesn't switch.

I have Nucleo-G071RB. I want to flash the LED LD4 using CMSIS. Use IAR 8.40I'm writing the following code: GPIOA->MODER |= 0x400; (set GPIO_MODER_MODE5_0). It's not working! In the debugging window, bit 11 doesn't change and the LD4 LED doesn't switc...

VTyut.1 by Associate
  • 2614 Views
  • 3 replies
  • 0 kudos

Resolved! STM32F070RBT Bootloading via USB

According to AN2606 section 12 we can use USB DFU bootloader as long we have HSE using a 24, 18, 16, 12, 8, 6, 4 MHz crystal. This is missing from section 3.3 of the datasheet. Is there a reason for this?

CWedg.1 by Associate III
  • 1012 Views
  • 2 replies
  • 0 kudos

Resolved! STM32H562 FLASH Prefetch and ICACHE

Hello,I am currently evaluating the STM32H562 device. This devices has an ICACHE (instruction cache) module.Does it make sense to enable both, the ICACHE module and the FLASH prefetch buffer? In the past I already worked with the G0, G4 and F4 series...

Resolved! STM32G473 extended CAN ID never even

I'm attempting to interface an STM32G473 with a VESC motor controller using CAN.I am successfully receiving status frames from the VESC controller, but when I transmit a frame to command it, the ID my scope reads in the frame is not always the same a...

SRP by Associate II
  • 3256 Views
  • 6 replies
  • 5 kudos

Resolved! De-interleaving DMA output from sequentially configured ADCs

I am using all 3 ADCs on an F765 to convert 16 channels of data at 50 ksps. Each ADC is configured to perform a sequence of conversions (5 on ADC1 and ADC2, 6 on ADC3), all triggered from the same timer. I have also configured them to ping-pong the d...

Nev by Associate II
  • 1972 Views
  • 8 replies
  • 0 kudos