STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...
In RM0456 section 73.4.3 OTG_HS core (p.3279) I found the following statement:"The OTG_HS receives the 60 MHz clock from the reset and clock controller (RCC). This is typically generated in the PLL associated with the HS PHY and enabled in the RCC. T...
I'm new to working with ADCs on STM32. I'm reading a rectified voltage using ADC with DMA on an STM32G0B1. I know the ADC conversion time from the datasheet but I want to compare the ADC's output with readings from an oscilloscope. I'm plotting the v...
Sorry to bring up the elephant in the room. I just reviewed the ST Q1 quarterly results from April and was astonished to not find anything related to lead times, shortages, or allocations.My company is in the Musical Instrument space. We work with a ...
Just started playing with FreeRTOS on a NUCLEO-H563ZI board using CMCIS OSv2. Why does osThreadGetState() translate eSuspended to osThreadBlocked? I suspended a thread and then checked its state with osThreadGetState() which reports the state as bloc...
Hello everyone!I have started a small journey to try to get started with eMMC memory and are trying to get it working.The end goal is to have a USB HS mass storage device eMMC working with a file system. (32gb or more) My current step that I'm stuck ...
Hi, I'm having a problem with unintentionally splitting a message I'm trying to send over the UART using DMA . I am using one function to send the message:const uint32_t max_value_of_counter_loop = 100; /* in case systick jams */volatile bool was_u1_...
Hi there,We use a STM32F723 controller and want to connect two external RAM devices.Now we have to select a RAM that fits to the FMC. What we can't find in the reference manual RM0431 is, if SDRAM-DDR functionality is provided or only SDRAM without D...
The STM32H7(4/5) documentation states that two of the ADCs on board can be used in dual ADC mode, so that their 16bit samples are read into the upper- and lower halfwords of a single 32bit register (ADCx_CDR), from where a single DMA can read them in...
Hi, is there anyone who can help me to understand the circuits of the x-nucleo-ihm08m1 ? Like explaining to me how the figure 5 does the analog conditiong and current protection.
Hello,Does anybody know what's the planned production release date for the STM32H563MIY3 WLCSP 125C MCU? I am considering it for a future design.Thanks
