STM32 MCUs Products

Ask questions, find answers, and share insights on STM32 products and their technical features.

cancel
Showing results for 
Search instead for 
Did you mean: 

Forum Posts

Resolved! DMA2D with SPI in STM32L4P5RG

Hi I want to improve the FPS of TFT when using SPI interface.I use SPI+DMA+QuadSPI PSRAM+QuadSPI Flash for now.I notice STM32L4P5RG has DMA2D.So can it use for SPI interface?Will it have any improvement when I refresh TFT?If it has, how to use it?

Problem with LSE on stm32l562xx

Hello. I've a problem regarding LSE On stm32l562xx mcu. Sometimes it boots, sometimes it doesn't "90 % of time it generates timeout Error" . and it takes too much time to boot up to 4 seconds. I've tried all your sdk initializations, also tried setti...

as0 by Associate II
  • 4329 Views
  • 11 replies
  • 0 kudos

STM32L431 Flashing fails if there is CAN bus activity

I find that flashing a program using openocd, STLink (using a Nucleo F446, or L474), to our custom board frequently fails when there is CAN bus activity. What is causing this?Our board has BOOT0 tied to ground. The SWD is gnd, data, clock, and connec...

DHase.1 by Associate III
  • 1459 Views
  • 5 replies
  • 1 kudos

Resolved! RTC freezes when STM32G030C8 is powered by VDD

I'm using the STM32G030C8 for one of my projects and i realize that in some cases the RTC stops when the power supply is up. While in VBAT supply the resonator works well and provide the correct date and time, but when i use the power supply the reso...

gtimmen by Associate II
  • 1441 Views
  • 5 replies
  • 3 kudos

Resolved! STM32H7 Independent Watchdog Timeout Limit

Per the presentation linked below, the independent watchdog timeout range for the SMT32H7 is from 125 microseconds to 32 seconds. Is 32 seconds a hard limit? We would like to increase this value.STM32H7-WDG_TIMERS-Independent Watchdog (IWDG)Thanks in...

westman by Associate
  • 732 Views
  • 1 replies
  • 2 kudos

STM32U575 RAM data retention in Standby mode

Hi,I am trying to make a program in which in the micro stm32u5 is stored in ram memory some data after activating the Sleep Mode. For this I have defined in the flash file the SRAM2 memory which is the one that is supposed to be in charge of this:   ...

Ifer by Associate
  • 785 Views
  • 1 replies
  • 0 kudos

Resolved! ADC1 and ADC2 interleaved mode using DMA + injected

Currently I'm able to run ADC1 and ADC2 in interleaved mode using seperate (on purpose) DMA channels for ADC1 and ADC2. To start I'm using:  SET_BIT(hadc2.Instance->CFGR, ADC_CFGR_DMAEN); //Enable DMA transfer for ADC slave (ADC12_CCR.MDMA = 0b00 -> ...

CyberNerd by Associate III
  • 895 Views
  • 1 replies
  • 0 kudos