stm32f401re nucleo: PLL configuration
Posted on November 26, 2015 at 13:54Hello everybody!I'm trying to configure the main PLL to generate the max clock frequency (84 MHz on this board), and I'm using the HSI as PLL source.I made some test:- test1: HCLK=70 MHzM=16N=140P=2AHB_PR=1APB1_PR...