Ask questions, find answers, and share insights on STM32 products and their technical features.
Posted on October 21, 2015 at 14:59Hello, why do the recent STM32Cube Headers still keep BSRRH/BSRRL in the GPIO_Typedef in STM32Cube_FW_F3_V1.3.0 while STM32Cube_FW_F2_V1.2.0 drops BSRRL/BSRRH in favour of BSRR as used in the other headers This ma...
Posted on October 11, 2015 at 15:07This is relation to my previous forum post [DEAD LINK /public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/STM32F030F4%20ADC%20strange%20behavio...
Posted on October 26, 2015 at 13:55Hi, I hope someone can help me. We do have some strange behaviour with our STM32F4-Discovery Boards. Currently we capture analog data on two channels. Both channels are configured equally. Despite equal configurati...
Posted on October 27, 2015 at 11:37hello everybody !!! I'm using ''__HAL_TIM_GET_FLAG'' on my STM32l051K6 for detect an overflow on my timer, but i don't know how much machine cycle it takes ?Could someone tell me how this function uses machine cycl...
Posted on July 23, 2015 at 12:19Hello. There is a bug in the cmsis_os.c file: at line 757: return xQueueCreate(queue_def->queue_sz, (uint32_t) sizeof(queue_def->item_sz)); sizeof(item_sz) is always 4, so all queues are created with element size = ...
Posted on October 26, 2015 at 14:47 On an stm32f411 Nucleo, I'm trying to generate a DMA request to transfer data from memory to the USART2 data register at every compare event (when CCR1 matches TIM3_CNT). To this end, I have, in order: ...
Posted on October 26, 2015 at 16:44ST Community - An application has the current design parameters for a Cortex M0 device STM32F030R8:CLK: 20MHz external xtal on (PF0 & PF1 RCC OSC) internal PLL to 40MHz (25ns).Regarding Timer 3, I want to create a ...
Posted on October 26, 2015 at 16:18ST Community - An application has the current design parameters for the STM32F030:CLK: 20MHz external xtal on (PF0 & PF1) internal PLL to 40MHz. Complete. MCO: 40MHz CLK/2 = 20MHz out on PA8 (MCO alternate function...
Posted on October 26, 2015 at 15:56Hello, what is Half-cycle access (FLASH_ACR_HLFCYA) for? It may be used with slow clocks ( < 8 MHz) and AHB divisior = 1.
Posted on October 11, 2015 at 15:24 Hello, I tried to test the I2C interface on a STM32: #include <stdio.h> #include <stdlib.h> #include ''diag/Trace.h'' #include ''stm32f4xx_hal.h'' #include ''stdint.h'' int main( int argc,...
