Posted on September 07, 2015 at 11:34Hello, I have some problems with FMC when I try to port my code from SMT32F407(with FSMC interface) to new project based on STM32F746(with FMC). The only changes I've made are timings(adapted to 216 MHz clock) an...
Posted on December 17, 2015 at 09:10I am using IAR EMBEDDED WORKBENCH 7.50.1.10273 (Common Components 7.3.1.3987)Audio application (which is located in ...\STM32Cube_FW_F4_V1.10.0\Projects\STM32469I Discovery\Applications\Audio\Audio_playback_and_re...
Posted on December 19, 2015 at 12:58Hi,I am using Nucleo board and Keil 5. I am using cubemx to configure the nucleo (STM32F103Rxx). My doubts are1. if i configured USART then, do i need to configure the pins (for USART) manually in code?2. If i con...
Posted on December 21, 2015 at 23:36Hi,I'm using STM32 micros for a while. Now I'm migrating and old firmware from a LPC17 cpu to a STM32F1 and I don't know if I can replicate one functionality.I need to start a timer that will generate a single fix...
Posted on December 22, 2015 at 09:13Dear ST team,I run into some problem with Ethernet due to some initialization missing. In my system I use an external DRAM for the bss section and the internal ram for the data which use DMA. The bss is initialize...
Posted on December 21, 2015 at 20:12I'm building a test program under STM32CubeMX 4.12.0 (with latest peripheral libraries as of 12/21/15) that uses the STM32F207's CRC peripheral, and I have discovered that the autogenerated code isn't enabling the...
Posted on December 22, 2015 at 02:06Hello! Referring to the CAN Networking sample codes in Cube MX F3 package, I tried it out by connecting 2 STM32F303 Eval Boards. I used a female-female connector to connect the two boards. However, I am not able t...
Posted on December 15, 2015 at 18:12Hi all, is it possible to get older version of CubeMX to track new issues? It would be excelent if there would be posibilty to choose which version you want to use.
Posted on December 17, 2015 at 20:28 The original post was too long to process during our migration. Please click on the attachment to read the original post.
Posted on December 21, 2015 at 17:46Clarification needed... When does the ADC EOC Flag get set? Before or after the ADC_DR write latency? ADC clock settings: Pclk/4 = 40MHz/4=10MHz(ADC_CLK 100nS). Write latency spec: 8.5 fpclk typ. (8.5 * 100ns = 8...
