Ask questions, find answers, and share insights on STM32 products and their technical features.
PART NO: STM32H743IIT6CUBE_IDE VER: 1.19.0SDK : STM32Cube FW_H7 V1.12.1LSE PART NO. : CM9V-T1A-32.768kHz-12.5pF-20PPM-TA-QCHello everyone,I am trying to use RTC on mentioned STM part number. I have enable LSE and configured the RTC.Currently i am not...
Hi! I am trying to muddle my way through a design that revolves around an STM32U5 MCU, and am specifically trying to think about ESD protection. I have been referencing AN5612, which quite helpfully provides lots of specific examples for various appl...
Hello,first let me start this post by mentioning that I'm still very much a beginner.I'm writing my own abstraction layer functions for the N657X0.While running my clock_config() function, I ran into an issue that I don't know how to fix. The functio...
Hello,I dug deeper into PSSI behavior, and and I observed unwanted behavior. From my point of view it is a bug.PSSI is configured as:OUTEN = 1 (transmit mode)CKPOL = 0 (outputs driven on rising edge, inputs sampled on falling edge)RDYPOL = 0 (0 at in...
Hello,I designed a custom PCB using the STM32F401RE (LQFP64), but I cannot connect to the MCU through SWD. I am using an ST-Link probe and the st-probe command-line tool.When I run the probe command, the ST-Link probe itself is detected, but the targ...
We are developing a STiROT/OEMuROT bootloader for a customer using the above chip. This is based on the STM32H7S78-DK sample. The customer has developed the main application and have added support to download a new firmware image over Ethernet. This ...
I'm trying to set up FSMC in muxed mode to read_write external NOR flash devices. Muxed pins goes through 2 8-bit latches 74HC574D.The problem is that currently i can barely read from external NOR and it's not accepting commands.Firstly HAL_NOR_Init(...
Hello ST,1. ds14258 Rev.6 Table 57 on p.163 specifies a positive I_inj of "N/A" for pins other than PA4, PA5, PB2, PB12,PC14, PC15, PD8, and PH2 (as opposed to a positive I_inj of "0 mA" in the row above for pins PA4, PA5, PB2, PB12, PC14, PC15, PD8,...
I found more issues. 1. Missing SRAMEN bit in RCC_AHBENR register. I think it is bit 9. See STM32U0 RM0503 page 54, RCC_AHBSMENR register and STM32F0 RM0091. With this new bit, reset value is: 0x0000 0300Also I think that it is missing SRAMRST bit ...
Hello,I would like to confirm how VBUS behaves in STM32 USB OTG depending on the Host/Device mode.Specifically, I would like to ask the following:When STM32 is configured as Host mode, should the STM32 source 5 V onto VBUS?When STM32 is configured as...
