About Yang Yang

Yang Yang · 2024-10-25

Hello, ST experts STM32U595VJT6 is used on the design. The OTG part of MCU works well on USB device mode. And it functions as USB flash disk. But when I check the logical level from OTG device status register(address offset is 0x808), there is somet...

Yang Yang · 2024-06-23

Hello, ST expert STM32F407 is used for our custom design. And htim2 play the role of precise timing base.When htim2->Instance.CNT = xx is used for setting a new counter start value for timer2, it seems that the new counter value does not functions i...

Yang Yang · 2024-06-14

Hello, ST expertE.g. GPIO PD4 functions as falling edge interrupt pin on STM32F407. Before the falling edge this interrupt is disabled by HAL_NVIC_DisableIRQ(EXTI4_IRQn). What happened if HAL_NVIC_EnableIRQ(EXTI4_IRQn) is executed after the falling ...

Yang Yang · 2024-04-12

Hello, ST expert CubeMX generated software framework is used for our STM32U595VJT6 based hardware design. It works well but for the low start up time. It takes almost 1 second between 3.3V is stable and the flag GPIO turns high in MX_GPIO_Init. Is th...

Yang Yang · 2024-03-11

Hello, ST experts STM32U595VJT6 is used on our own HW design. There is external SD3.0 compliant level translator NVT4857UK to help to work on UHSI mode. Everything is fine when SDIO clock sets as 96MHz or lower. But when the SDIO clock is higher than...

Yang Yang · 2024-10-28

Hi, @FBL You mean DEVLNSTS[1:0] can be read not only in interrupts but also in any time during suspend?But I don't quite understand why USB_D- is about 0V, USB_D+ is about 3.3V, DEVLNSTS[0] is high logical level and DEVLNSTS[1] is low logical level...

Yang Yang · 2024-10-27

Hello There is another update on this thread. It is found that the read of OTG_DSTS is not done on interrupts from the device all interrupts(OTG_DAINT) reigster. Is that the key issue?And if it is so, why the DEVLNSTS[0](USB_D-) is always logical hig...

Yang Yang · 2024-10-27

Hi, @FBL Another question about this thread. Does DEVLNSTS[1:0] represents the realtime logical level of USB_D+ and USB_D-? There are very few discriptions about DEVLNSTS[1:0] on STM32U5's user manual. BRYang

Yang Yang · 2024-10-27

Hi, @FBL The divice is configured in High Speed Mode. Yes, the logic stat of DEVLNSTS is not deterministic. Cube MX generate the code framework as the picture below. USBX and ThreadX are used in the software.For the USB traffic, because the probe o...

Yang Yang · 2024-10-25

There is a update on this thread. The DEVLNSTS[0] is occasionally logic high level when USB cable is plugged in. (The possibillity is about 2%, 50 measures, 1 logical high, 49 logical low).

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The DEVLNSTS[1:0] of OTG device status register seems to show a wrong logic level

what is the timing diagram about writing TIMx_CNT register

a problem about interrupt enable after the interrupt happened

stm32u5 start up time too long

the sdio of stm32u595 can not work at 128MHz or higher SDIO clock frequency

Re: The DEVLNSTS[1:0] of OTG device status register seems to show a wrong logic level

Re: The DEVLNSTS[1:0] of OTG device status register seems to show a wrong logic level

Re: The DEVLNSTS[1:0] of OTG device status register seems to show a wrong logic level

Re: The DEVLNSTS[1:0] of OTG device status register seems to show a wrong logic level

Re: The DEVLNSTS[1:0] of OTG device status register seems to show a wrong logic level