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New to external Sram Sdram

Posted on January 17, 2017 at 09:08Hello all We are new to external SRam and Sdram so I have some question we could don't verify the answer maybe because of language or lack of knowledge.we need to add external ram to stm32f4  and stm32f7So how to c...

HAL_UART_Transmit_DMA/IT Returning STATE_READY too fast

Posted on January 13, 2017 at 23:27 Preface: I have been working with the DMA/IT TX/RX successfully and this is the first I've ran into this problem. When trying to transmit back to back, my second transmission cuts off half of the first. Now,...

Sam V by • Associate II
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UART: Communicate faster with a PC ?

Posted on January 18, 2017 at 16:54PC computer  seem to allow  serial communication up to 256,000 bps over USBBut the ARM based Cortex M7 like STM32F746xx have 25 communication interfacessome of them capable of up to 27 Mbit/s Is there a way to com...

Reset Reason STM32Fx

Posted on January 18, 2017 at 09:45Hi,is it ensured that there is just one bit set in the RCC_CSR register when it is cleared and afterwards a certain reset occurs? Or is there a case so that more than one reset reason bit becomes set?There is no st...

sascha23 by • Associate II
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STM32F746 BSP

Posted on January 18, 2017 at 04:19I am tring to figure out how to use the BSP for my stm32f746G-Disco board.  I have worked through several issues from setting the STM32CubeMX and getting the files in the correct place.  I have run into the problem...

ray23 by • Associate II
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Resolved! SPI 1 does not work after migrating from stm32f1 to stm32f2

Posted on January 18, 2017 at 05:44Hello folks,I am working to migrate my firmware from stm32f103 to stm32f20f family, for that I have gone through the guide provide by st http://www.st.com/content/ccc/resource/technical/document/application_note/27...

rutvij by • Associate II
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STM32F4 how to support two network interface

Posted on January 17, 2017 at 04:08Hi:I use STM32F4 series and it works OK for one network PHY (using LwIP). As I know the F4 MAC interface can read/write  more than one PHY's. However only one set of MII/RMII interface pins and MAC hardware, imply ...

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