Interfacing STM32 with External 512kx16 SRAM, 8bit data only accessible per one address of RAM

[vishal patel]

Posted on February 25, 2017 at 11:44

Hi,I have STM32F4 interfaced with the external SRAM sized 512kx16 array. Now what I believe is (Pls correct me if i am wrong), Pointing to Every incremental Address should give me 16bit data. because SRAM is interfaced with 16bit wide data bus (non multiplexed)

For Example: 0x64000000 is the base address of my external SRAM. And I want to write hello, to this RAM, then It should happen like...

on 0x64000000 location, data should be written, 'H' 'E' &

on 0x64000001 location, data should be written, 'L' 'L' &

on 0x64000002 location, data should be written, 'O' 0xff .

And the same is should be getting in read back. But What actually occurs is

on 0x64000000 location, data iswritten, 'H' 'E' &

on 0x64000001 location, data is written, 'E' 'L' &

on 0x64000002 location, data

is

written, 'L' 'L' &

on 0x64000003 location, data is written, 'L' 'O' &

on 0x64000004 location, data is written, 'O' 0xff .

So If I want to get the write data, I will have to read back 16 bit data from location

0x64000000,0x64000002, and 0x64000

Can Anyone Has the experience of interfacing 512kx16bit array SRAM ? and facing the similar issues ??

#external-ram #sram #stm32 #dma #fsmc Note: this post was migrated and contained many threaded conversations, some content may be missing.

[T J]

Posted on February 25, 2017 at 16:16

The SRAM/SDRAM/FLASH all have a unique address for each Byte...

it is a byte addressing scheme...

Usually you would declare as:

//align (2);             // this is done by default for int16_t

int16_t Variable1;

char array(7);      // 1 byte remains unused

int16_t Variable2;

[Tesla DeLorean]

Posted on February 25, 2017 at 16:28

How do you suppose you can write 'H' and 'E' into the same byte?

You'd need to treat the memory the same regardless of how it is physically bused. 16-bit wide means you can write two bytes at ones, but they still consume two bytes, so the stride would be two to the next pair

ie

Write 'H' together with 'E' to 0x64000000

Write 'L' together with 'L' to 0x64000002

[world04]

Posted on February 26, 2017 at 16:04

The Bus connection and the access of them by the CPU kernal are independed and unknown by the programming language. In every case, you need to take care about the alignment of your declared variables or structures, if you wanna do a direct register or memory access.  How wide the bus is and how many clock cycles the mpu needs to do, is hidden by the program. The memory storage is byte-wide organized. As an example - a charcter like ' ' is coded by ASCII in 0x20 or dec 32 and could be coded by just 7 bit's - does the MPU wrote just 7 bit's into the memory to store them, or store it 8 bit's? 

if a value is 32 Bit's wide, the clock cylces that the mpu need's to store this 4 byte wide value depended on the used databus bit's of the memeory who are connected to the MPU. In every case, you need to declare the useddatabus bit's in the  FSMC definition, before you can use them and how fast this is possible. The fastest way to get or store data is of course a 32 bit connectivity for data. The thumb command set of the ARM is traditionaly just 16bit wide.  

[vishal patel]

Posted on February 27, 2017 at 07:51

Thanks all For Replies,

I am using AS6C8016, which is 512kx16bit array SRAM. It has A0-A18 Address bus, so technically I can address only 524287 location, lets say 512K, And now according to you, If I can access 1 byte only per one location, then How can I access 1 MByte memory, [which is as per their data sheet, 8,388,608-bit/8MBit/1Mbyte].

It has UB/LB control pins too, but I think It is for the 16bit-data bus access control only. Not for the Memory array control of the SRAM,  right ?

[T J]

Posted on February 27, 2017 at 08:24

<edited after understanding>

Usually you do connect the /UB and /LB pins, yes.

I checked the cubeMX file. attached

the 100pin processor does not give you the functionality.

I went to the 144 pin.

2^ 19 =512k (A0-A18 is 19 pins)

2^ 20 = 1M (A0-A18 with UB and LB strobes)

The pins /UB and /LB are used like another A0 physically.

Wire /UB, /LB and A0-A18, from the MCU to the SRAM, then you will have the necessary 20 address pins.

see link below:-

.

/external-link.jspa?url=http%3A%2F%2Fwww.st.com%2Fcontent%2Fccc%2Fresource%2Ftechnical%2Fdocument%2Fapplication_note%2F27%2Fbf%2Ff5%2Fe8%2Fd7%2F82%2F44%2F6f%2FCD002004pdf%2Ffiles%2FCD002004pdf%2Fjcr%3Acontent%2Ftranslations%2Fen.CD002004pdf

Thanks to

https://community.st.com/people/Kaltofen.Jupp?et=watches.email.thread

for the excellent work. ________________ Attachments : F417ZGT 144 pin SRAM.ioc.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hyry&d=%2Fa%2F0X0000000bDN%2FV7C74hNp8tV5cPIeDYjZygTL9E1cI3fJMxx0TQohQo8&asPdf=false

[world04]

Posted on February 27, 2017 at 09:28

 ,

 ,

Well, you have a missunderstanding between the access of the CPU and the Program who access to the external memory.

Assume that one address is just for one byte, not for a word of dword. The address range is byte oriented - the smallest

unit the cpu can read or write to a memory.  ,The cpu is able to read/write 32bit data in one access - but you need the start address of the first byte to do this. How this is physical done  ,is depend on the used mpu implementation.

 ,

every memory address stays for only one byte - how wide the physical is done by real to the memory is depended by the fsmc definition you need to setup.

I had added an example snipped of an STM32F7 Disco board, who are uses SDRAM and mapped them into the data address room of the CPU. The blue marked up line defines the available bus width of the memory for the cpu.

The cpu now know, how wide the access could be and select the fitted method to gain access to the memory.

 ,

it allways access with 32bit - even you need to manipulate just 8 bit. It need's to do this in two cycles and this consumes time. it's a compromise between the costs for using 32 lines on the pcb and memory device and the loss of performance. ARM had done the job quite well and this method to gain access to smaller bus with is quite fast and you don ♯ t got a big penalty doing like this, but in some cases, this is not the best method - in other cases, you have no other alternative (TFT, I/O Device) ,

//HAL_FMC_MspInit(), // GPIO ALTERNATE FUNCTION ROUTING

/** Perform the SDRAM1 memory initialization sequence */

 ,

hsdram1.Instance  , , , , , , , , , , , , , , , , , , , , , , , ,= ,FMC_SDRAM_DEVICE, /* hsdram1.Init */

 ,

hsdram1.Init.SDBank  , , , , , , , , , , , , , , , , , ,= FMC_SDRAM_BANK1,

 ,

hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8,

 ,

hsdram1.Init.RowBitsNumber  , , , , , ,= FMC_SDRAM_ROW_BITS_NUM_12,

 ,

hsdram1.Init.MemoryDataWidth  , = FMC_SDRAM_MEM_BUS_WIDTH_16,

 ,

hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4,

 ,

hsdram1.Init.CASLatency  , , , , , , , , , , , ,= FMC_SDRAM_CAS_LATENCY_1,

 ,

hsdram1.Init.WriteProtection  , , , , , , , , ,= FMC_SDRAM_WRITE_PROTECTION_DISABLE,

 ,

hsdram1.Init.SDClockPeriod  , , , , , ,= FMC_SDRAM_CLOCK_DISABLE,

 ,

hsdram1.Init.ReadBurst , , , , , , , , , , , , = FMC_SDRAM_RBURST_DISABLE,

 ,

hsdram1.Init.ReadPipeDelay , , , = FMC_SDRAM_RPIPE_DELAY_0,

[vishal patel]

Posted on February 27, 2017 at 09:37

Thanks for details .

I understood that. 

But the question is how can I access whole 1Mbyte of SRAM with just A0-A18 Address lines ? If I can have 1 byte per 1 memory location, then I will have an access for only 524287 bytes. But Data sheet says its 1Mbyte.

[world04]

Posted on February 27, 2017 at 21:17

Ok, your example has a wrong address range declaration - not 20Bit, just 19Bit. Connect the lines UB# and UL# to NBL0 and NBL1.The sram address lines A0 to A18 should connect with A0 to A18 of the MPU. The 'ByteEnable' lines are used by this SRAM config and map's NBL0 and NBL1 to the control bus. To use them as an A0 line to flip the low- and high-byte's will not work.

I had not further checked your system timing that the MXCube generate, but i have cleanup the code to get a more overview and comment some lines of code to mak up them for what this stay's for and the purpose of them.

http://www.st.com/content/ccc/resource/technical/document/application_note/27/bf/f5/e8/d7/82/44/6f/CD002004pdf/files/CD002004pdf/jcr:content/translations/en.CD002004pdf

.The example link points to a document from st where the wiring is done and the schematic is useful. I had used the HAL-lib and not the stdLib, that's often used up to F4 familiy controllers. This is more detailed and better fixed and upward compatible if you may use an newer controller's like the F7, where StdLib's are not available.

I will hope this will help's you to solve the problem finaly. If you had done this issue, lease release a detailed notice how you have done this. I had spend near one hour to recherche this replay - it would be nice for all other here, to find a complete thread.

Just a sentence to HAL and STDLIB for others:

I know there are always programmers out there who say, that you should neither use the one nor the other and instead of the better the register directly served - best in Assembler. Well, it is forgiven me, but I am not interested in any further discussion on the usefulness of this Libs. If you do not want to use it, you just have to leave it - no one is tamed to do so.

________________ Attachments : TEST.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HyoH&d=%2Fa%2F0X0000000bDM%2Fc2t_fKIsuyvqVt3MGHmiAP6y_6HR94Foidg1KLjhgq4&asPdf=false

[Tesla DeLorean]

Posted on February 27, 2017 at 22:29

The A0 bit from the CPU perspective is not emitted, the STM32 shifts the address bus down so the internal A1..A19 appear as A0..A18 from the memories perspective.

It accesses two bytes at once, so by accessing 524288 16-bit words, you have access to 1048576 bytes.

The byte lanes and muxing on the interface side manages the access of bytes/words

Think of it as a two lane motorway, twice as much traffic can flow, the distance between the towns doesn't change, ie 512K car lengths, but the capacity would be 1024K cars