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Posted on September 26, 2017 at 11:58 Hi there, I'm working on STM32F103 MCU and i need to compute the powerof a value. I use the math.h library but I'm looking for a more optimised library, if it's exists. Is there a better way to compute th...
Posted on September 26, 2017 at 02:05Hello I trying to build 14 Khz bandpass filter on stm32f103 any help will be appreciated. Ted
Posted on September 22, 2017 at 11:34Hi!For my system I need to send and receive a 1Mbps Manchester encoded signal do you guys maybe have an idea of how I could accomplish this with the STM32 or maybe there is example software I could use. Or maybe ...
Posted on September 26, 2017 at 17:59Hi,how can I report bug found in STM32H7 sources? Do you have any issue reporting system?I found bug in HAL_SPI_Transmit_DMA() function. I use SPI channel in 'Transmit only mode' (configured using STM32CubeMX) so...
Posted on September 25, 2017 at 11:35Hello,the last two line on page 109 rm0433 rev 3 chapter 2.3 read: The ECC mechanism is based on the SECDED algorithm. It supports single- and double- error correction.The description is wrong. It should read lik...
Posted on September 26, 2017 at 13:52Is there a way to find out the reset cause by reading register or such, on STM32F429ZI Micro?#reset-cause
Posted on September 25, 2017 at 10:31Hello! Have some problem with UART on STM Nucleo L476RG. We need to transmit bytes from Nucleo to Raspberry (needed to output in program on Raspberry count-speed; it depends on frequency on Nucleo, that we want t...
Posted on May 08, 2017 at 13:17Hello,the system headers from STM32Cube_FW_F7_V1.7.0 use#define FLASHSIZE_BASE 0x1FF0F442Ufor all families. However the RM0431 Rev1 tells 0x1FF07A22.Accessing 0x1FF0F442 on a F723_disco crashed...Please recheck and cor...
Posted on March 27, 2017 at 05:51Bug in Cube_F7_1.6 stm32f7xx_hal_rcc.cHAL_RCC_GetOscConfig(); does not populate RCC_OscInitStruct.PLL.PLLR with a value under any circumstance.It should have a value between 2 and 7 if defined (STM32F765xx) || define...
Posted on September 18, 2017 at 13:15ADC1 converts every 500us 5 analog channels ( ADC10/11/12/13/14) and write the result via DMA1 to internal SRAM (ADResult[5]) in this order [ ADC10,ADC11,ADC12,ADC13,ADC14]. This works fine, but randomly after ...
