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Posted on June 27, 2016 at 16:07Just thought I'd save people some time if they are trying to get the CRC engine on the F4/F7 to produce the same results as most online calculators. If you are using CubeMX to configure your CRC, you need to specify t...
Posted on April 24, 2018 at 17:35I came across a rare issue where a previously failed flash operation would cause a subsequent operation to fail as well. I tracked it down to stm32f4xx_hal_flash.c::HAL_Flash_Program()When the function calls FLASH_W...
Posted on April 24, 2018 at 10:13Hi,I'm trying to set the UART baud rate to 600 on a Nucleo F070RB board to communicate with the CS5490 chip. (https://www.cirrus.com/products/cs5490/)I've only managed to go down to 732 baud rate. Anything below, it ...
Posted on March 25, 2018 at 16:45Hello, I have question about CAN on STM32F429-DISCO board.I found that CAN1 is shared with display control and CAN2 with on-chip debugger. In comments for this video (/external-link.jspa?url=https%3A%2F%2Fwww.youtube...
Posted on April 24, 2018 at 15:37Hi, i am use stm32f105RB MCU and in that my I2S frquncy was set minimum 8 MHZ ,bellowed 8 is possible or not ?and I2S interface with MICmic link ==>www.knowles.com/kor/content/download/5988/.../4/.../SPH0645LM4H-BRe...
Posted on April 24, 2018 at 02:33That it's a clock which could be used for SAI1 is explained above at PLLP; still, the signal's name is PLLSAI2CLK, however confusing that is.JW
Posted on April 24, 2018 at 11:35Hello there,I am using STM32L4 family MCU. I was wondering either it is possible to configure a pin to act as 2 configurations. In my situation, I am trying to make the pin PA0 to act as UART2 CTS line and External i...
Posted on February 08, 2017 at 18:29I need to test a fw that plays with uart output/input operating in asynch mode. Although this mcu has 2 uart and 3 usart (asynch/synch configurable) ports the only available USART module is USART2 port in PD5, PD6...
Posted on January 16, 2018 at 12:26These clearly contradict. So, which one of them is true?JW
Posted on April 24, 2018 at 13:45Ok, this is half way simple but I have not found any good answer yet.I have some data in EEPROM that needs to be shielded from SWD accesses (and some later on at runtime in SRAM). Direct SWD reads can be to EEPROM ca...
