Posted on October 28, 2017 at 11:29Does it save all the registers of the current process before executing the ISR? If so, how does it save the registers? Does it do it by pushing all registers in stack?#stm32f103xx #interrupts
Posted on October 27, 2017 at 19:36What is Dual Address Mode in I2C Handle? #i2c-addressing
Posted on October 25, 2017 at 06:56The original post was too long to process during our migration. Please click on the attachment to read the original post.
Posted on October 28, 2017 at 00:57I am using M41T81S chip for a RTC.I am having a issue keeping a time on power down.I borrowed the circuit from following location.http://www.niell.org/nixie_3/NixieClock5-1.bmp Instead of C2 in the picture, I am us...
Posted on October 27, 2017 at 00:54I need to create two synchronized signals. I'd like to use a PWM output for one, and to have the software create the second signal based on an interrupt from the same clock used to create the PWM output.I'd like t...
Posted on October 23, 2017 at 13:54On an STM32L100 series MCU: Assume that initially, Systick priority is set below EXTI15_10During the EXTI15_10 ISR: Systick occurs, but its interrupt is held because we're in a higher-prio interrupt;I then chan...
Posted on October 26, 2017 at 22:43 Because IDE does not like nested comments. I am commenting several lines of example code but some idiot has put every other line an one line a /* */ comment. Fix that software please. Not like this: /...
Posted on April 06, 2017 at 13:36Hi,I have a STM32F303 Nucleo-144 Development Kit and struggling to figure out which IDE to use. This is first project with Cortex-M micro-controller and I have a few queries:* If somebody who is aware of the software...
Posted on October 19, 2017 at 09:53Greetings people,I was wondering if the SRAM by CY62177EV30 is compatible with the FMC on STM32L496AEI with 20 bit address width and 16 bit data width.I can only use 20 bits from the address bus because of pin mul...
Posted on October 23, 2017 at 10:49I have a question about the stm32f103xx. I want to know how it boots from Embeded SRAM. I have known that the IBUS of Cortex-M3 can't access the SRAM from the reference manual. When boots from the SRAM, how Cortex...
