Resolved! STMF4 USB OTG HS with embedded PHY clocks
Posted on May 03, 2018 at 23:59Can someone explain me how USB HS is clocked, when using embedded PHY?
Forum Posts
Resolved! STM32L4 ISR source
Posted on May 07, 2018 at 18:26Hi,Is there any doc mention about STM32L4 (STM32L4996 and STM32L4A6) ISR source? The doc I found from both ST and ARM reference manual do seems list all of the ISR source.Thanks,****Note: this post was migrated and con...
PCROP Confusion
Posted on May 09, 2018 at 00:54I understand that there have been many threads about PCROP here. I am trying to understand the logic behind having to build code using mpure-code on gcc or the equivalent on other compilers that allows the avoidance of...
MPU regions and DMA
Posted on May 08, 2018 at 23:43I am confused over the inability to successfully setup an MPU region for the area that the DMA is using. I am trying to get around having to use Clean and Invalidate Cache like so to guaranty the data is passed correc...
How use to nandflash on usbdevice?
Posted on May 08, 2018 at 21:03I use STM32F429IG, MT29F4G08ABADAWP that have been tested nandflash alright.I want nandflash as usb device on WINDOWS10.So, I setting USB_DEVICE and mass Storage Class and use example 'STM32_USB-FS-Device_Lib_V4.1.0'.F...
Simulink error, STM32-MAT package, Function call from timer interrupt
Posted on August 25, 2017 at 10:09 I am following the tutorial that comes with the STM32-MAT package that deals with setting a basic block diagram to run on an STM32 target. In the simulink system I have used the predefined STM32 timer block and se...
Resolved! STM32F217 Revision 2 Bootloader
Posted on May 08, 2018 at 20:36Hi,I have a STM3221G-EVAL board with the STM32F217IGH6 and am trying to program over CAN. I checked the revision code on the chip to see what version bootloader it has and found it was a revision '2' chip. I can't find...
Problem with switching-off AHB bus to reduce power consumption
Posted on May 08, 2018 at 21:30Hi,I have a question... We use STM32F303 MCU and have configured a programmable voltage detector (PVD) to 2.9 V. At power-off interrupt is triggered and we have time till 2 V to store some diagnostic data into flash (f...
DMA from internal SRAM to FMC missing first byte
Posted on April 30, 2018 at 03:07 I'm using a Nucleo -F722ZE to interface with an FPGA. The instruction and data cache are disabled. I have timer interrupts to set off the DMA at specific times with 128 bytes per transfer. No matter how I set up th...
Resolved! stm32f407 i2s interface sync in slave mode
Posted on July 17, 2015 at 10:58Hello, I'd like to know if there is a 'magical' way to syncronize the bit stream with the channel signal in the i2s receivers. I don't have control on the external stream ( slave mode), so the serial clock is free run...
