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Resolved! SWO frequency?

In my debugger settings I got there is some SWO frequency difference means before 2 or 3 days its frequency value is 10Mhz but now it is only 2Mhz and from last days I have getting some errors. So plz tell me that such errors are coming due to this ...

LACTIC by Associate II
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Resolved! What is the latest STM32F103RBT6 MCU revision available?

Hi everyone,I recently found myself having spent a lot of time working to get I2C to work on the STM32F103RBT6 (the problem: I2C begins life in the BUSY state).This is apparently due to an ADC noise problem, as described in this errata (p. 26):https:...

STM32 UART basic comunication

Hi,my first example for RS232 communication and my first problem.I have this output in the terminal:5 ''! Ëå˙˙˙ <00> 5 ''! Ëå˙˙˙ <00> 5 ''! Ëå˙˙˙ <00> 5 ''! Ëå˙˙˙ <00> 5 ''! Ëå˙ <00> 5 ''! Ë <00> 5 ''! Ëå˙˙˙ <00> 5 ''! Ëåë <00> 5 ''! Ëåë <00> 5 ''! ë...

JNova.0 by Associate III
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STM32F769BI ADC_DMA interrupt causing debug stop

​​​​Hello, I am using the Stm32F769BI MCU.I am receiving 3 ADC channels through DMA.My problem is that debugging stops in the middle due to HAL_ADC_IRQHandler during debugging.To debug again, I must press the Run button again.I want to know why inter...

syoon.10 by Associate II
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  • 4 replies
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SPI: delay between write to TXDR and start of clock

Hello ,With SPI (SPI2 in my case) I experience a delay between a wite to TXDR and the start of the SCK activity in case of an empty TX fifo. It seems to be something like 5 SCK periods, so it changes with SCK frequency but this ratio remains. I check...

STM32L476 SPI half duplex receive clock

I configured the SPI2 port for bidirectional (BIDIMODE = 1) and rx (BIDIOE = 0), then enabled the port (SPE = 1). According to the RM the enable should immediately start sending clock pulses out the SCK pin and read data on the MOSI pin, since it is...