STM32 MCUs Products

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Resolved! STM32F429IGT6 was not working after a few cycles

When I upload my code the controller it was working fine for few cycles after that it gets stuck somewhere else and the code is not running. I checked it with the debugging mode in that when I run the code is working fine and when it gets struck I st...

AChan.15 by Associate II
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X-NUCLEO-53L1A1 SEGGER JLINK or ST-LINK?

Hi all,I've downloaded X-CUBE-53L1A1 software package and found in its debug configuration SEGGER J-LINK as Debug Probe. I'm using Nucleo F401RE.My question is: Is SEGGER J-LINK distribuited by ST? Or I have to change the probe to ST-Link? Thanks

How to measure VBAT, Tempsensor and VREFINT on STM32H753IIK?

I have single channel ADC measurements on ADC1 and ADC2 working with an STM32H753IIK.I need to measure VBAT, Tempsensor and VREFINT, which the source code says is ONLY on ADC3.I generated the following init code:void MX_ADC3_Init(void) { ADC_Channe...

MRex by Associate III
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  • 1 replies
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STM32F427 I2C Master Transmit - Restart - Issue

I am trying to modify my own I2C driver (I don't use Cube) - to talk to a BQ32000 device - it's a I2C RTC chip.The protocol is shown in the picture below.The protocol to read requires a "restart" after sending the chip's address and sub-address to es...

Joe.H by Senior
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  • 1 replies
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FSMC with Synchronous Memory

Posted on September 02, 2014 at 02:20I'm trying to connect from an STM32's FSMC to block-RAM inside an FPGA. Since this type of memory is synchronous, I need to expose the FSMC clock to the FPGA.At the moment I have an STM32F4-Discovery connected to...

dohzer by Associate II
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  • 9 replies
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ADC noisy with external clock on Nucleo F303RE ??

Hello,I have an application that reads a couple of ADC channels. each time through the main loop. There's no It's a blocking ADC read so nothing else is going on when I'm reading the 2 channels. For testing purposes I have a 3V battery attached to...

Queries on QSPI, used MCU stm32l4kc

The MCU qspi peripheral is connected to serial NOR flash. Along with these connection the same qspi individual data pins are connected to 3 individual Altera FPGA for booting purpose.qspi clock is common for all 3 FPGA.The following operation which a...