STM32 MCUs Products

STM32F7xx --> Undefined Reference to 'HAL_UART_Transmit'

Good afternoon,I recently started working with TouchGFX and encountered a problem while flashing the programm on my board STM32F746NGH6 (with the display: ETEM043005XDH6)After reading & understanding the code of the examples as well as building my ow...

I use STM32H742xI/G and I used the internal RAM to buffer for the display and buffer for keep data and the RAM is devided and i cant to extend the buffer of the keep data cause its passed from the memory part how i solve it?

UART/USART buffer is receiving garbage character after this sequence 1.Turning off power to RS232 2. Deinit Uart 3.Turning on power to RS232 4.Init Uart

UART buffer receives garbage character(first character) after power on reset to the module connected through UART? Is this expected?But while scoping RX pin,any character is not seen.

Unexpected performance when enabling cache with SRAM / external SDRAM.

I am using STM32F7508-DK and comparing the memory performance of its internal SRAM vs. the external SDRAM connected to FMC (starting from 0xC000_0000).When I turn on the cache, the performance behavior is unexpected. Especially, The external SDRAM is...

I followed the video instructions to start with idw04a1 on nucleo stm32L476 but i didn't get readable chars in Tera Term VT as shown in the video. I recieve special sign's. My setting is 112500, 8,N,1.

STM32L476deep sleep cannot set pwr_cr1 register bits.

Hi, i am trying to get stm32l476RET6 to deep sleep ( shutdown or standby mode) following mbed examples, but the processors power consumption i measure is not even close at the correct consumption in these modes.At some point, befote WFI() function,...

Synchronizing SPI in STM32F107

Hello,In my project, I connected two MCUs to each other (MISO->MISO, MOSI->MOSI, SCK->SCK). I define a new pin as the CS pin (PORTC.10). But in my receiver the sequence is wrong. Here is my code( For example I send 1234 but I get something else, some...

COMP and OPAMP clock enable missing from RCC chapter in 'F3 RMs

Given similar memory mapping, COMP and OPAMP (where applicable) is bound to SYSCFG in the various 'F3 models. However, there's no information of the clock enable for these modules in the related RMs. It's presumably enabled by RCC_APB2ENR.SYSCFGEN, b...