Resolved! How is the FMC supposed to behave when a slow write to one address is followed by a read from another address?
I have a problem accessing a SRAM connected via a 16bit databus to the FMC on an STM32F469. The processor is running 168MHz, and the FMC configuration is this: hsram1.Instance = FMC_NORSRAM_DEVICE; hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE...