NUCLEO-F103RB with STM32F103RBI want to use the DMA in a burst mode to write data from buffer in RAM to the TIM1_CCR1,2,3,4? that are in PWM mode. DMA burst transaction is requested on the TIM1 Update (UEV). Number of transactions in Burst mode is se...
I want to use RTC module in STM32. Eventhough i try to update the date and time registers, their values are not updated. I have given my code. I would be thankful, if someone can point out what is the wrong with my procedure. uint32_t _Time_Tens=0,_T...
Hello! I'm trying to use a custom PCB STM32L475 with the touch sensing library based on the 1 touch example there is available for the L4xx.I've configured the PC8 pin as TSC_G4_IO3 (as sampling pin) and both PC6 and PC7 as TSC_G4_IO1 and TSC_G4_IO2 ...
Hello, in my Application when i put my stm32 in deep sleep mode, i want to excute a task as an interrupt! is this possible ? if yes how? Thank you.
Can we use the reserved location of IVT as defined below 0x08000000__vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler ...
Hello Community,This post purpose is to inform you that the STM32G4 Flash is recharacterized. The Flash speed is increased from 20MHz to 34MHz in boost mode and to 30MHz in normal mode.Thus, the maximum number of wait-states is reduced from 8 to 4 w...
Hello, i read the UM2577 pdf, the user manual for the Discovery kit with STM32G474RE MCU (B-G474E-DPOW1 board). On page 29, chapter 13.3, an audio class-D amplifier example with separate application note is mentioned. Where can i find this app note a...
I set up Timer1 Ch4 and Timer2 Ch4 to toggle their Pins (PE14 and PE11) on Capture Compare. I use this as a step signal for stepper drivers with high microstepping (256x). I recognized that when I activate the interrupts to count the number of pulse...
Is there an LL example to enable the backup ram. This doesn't work: // Enable PWR clock LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); // Enable Backup ram clock LL_APB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_BKPSRAM); LL_APB1_GRP1_Enabl...