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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Weird problem with UART

I work with STM32L475.First I configure UARTint main(void) { /* Configure the system clock to 80 MHz */ SystemClock_Config(); GPIO_Setup();   USART_Setup(UART4, 115200);   USART_SendInt(UART4, 1234, 1); USART_SendInt(UART4, 0,...

STM32H743: what is the source of adc_hclk?

The reference manual explains how I can select between adc_hclk and adc_ker_ck_input as the clock for the ADC but I can't find what the source is for adc_hclk. It is one of the AHB or APB peripheral clocks but which one? Nowhere in the manual can I f...

PMath.4 by Senior III
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Configure SRAM as non-cacheable in MPU

Hello,In stm32h7 I see in the "System architecture" diagram that SRAM3,SRAM2,SRAM1 are not passing through the cache.Yet, it seems that when using SRAM3 with DMA I must configure it as non-cacheable, otherwise I get junk in data.Can anyone please exp...

ranran by Senior II
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I am trying to adapt the "USART_Communication_TxRx_DMA USART Transmitter/Receiver example" to my custom hardware using a STM32F439ZIT6 processor.

I'm trying to get this example to work with my custom hardware. The TX works fine. I can't get the RX to work.* This example was developed for the NUCLEO-F411RE board and my processor is an STM32F439ZIT6, not F411. Could this be the problem?* I ha...

svick.1 by Associate II
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