Resolved! IWDG reset and data retention
Hi following a reset by the IWDG, does the SRAM1 or SRAM2 keep their content?Thanks
Hi following a reset by the IWDG, does the SRAM1 or SRAM2 keep their content?Thanks
I'm trying to set up SPI transfer via DMA which is triggered by LPTIM1 on STM32H745IIK6. Unfortunately for some reason, no SPI activity is present regardless of the config register values, which seem to be correct. Here's the LPTIM1 and DMA1 config:A...
The interrupt vector table lists TIM3-TIM7 as having the acronym TIM2.
Hello,I am designing an embedded system with these parts:A Low-Power STM32F091RCT6 microcontrollerEC25 LTE/GPRS moduleA 16 Mbit serial flash (W25Q128JV)After each reset, the microcontroller should check if a new version of firmware is available. If s...
Hi,I'm working with stm32H743zi (Nucleo-144) , I have a device that transmitting data via SPI to my stm32H7, the problem is that the device sending data with a variable length that I have no idea about it and there is no way to receive the length bef...
Hi all,I have a complex system with several STM32H743 processors, 1 Master, 6 Slave processors. The Master sequentially reads data from all Slaves via Interrupt handling. SPI clock speed is 16 MHz, access to data reads (108 Bytes each Read) every 10 ...
How do I have to set the configuration of the FDCAN Message RAM Start Adresses correctly in order to use 2 CANFDs simultaneously?Is there an example which shows a correct initialisation? The default samples initialize all start Adresses to 0, but thi...
Dear friends,I'm setting a differential ADC input for my application.The Positive voltage connects to ADC1_IN1 and the Negative connects to ADC1_IN2.When I reading the 0V, the result I get is 1583 values of ADC (It is the raw data, I did not convert ...