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Resolved! STM32G0x1 external interrupt from PE possible?

My target device is a STM32G0B1VE which has PE but according to RM0444 Reference manual for STM32G0x1 chips the description of EXTI_EXTICRx register says that combination for PE is not present (reserved). Is it really no possible to use PE for an ext...

JOtru.1 by Associate
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Unique ID STM32F103xx vs STM32F0x1

Dear community, RM0091 (STM32F0x1) describes the structure of a 96-bit unique ID which consists of the lot number, wafer number, and wafer coordinates. RM0008 (STM32F103xx) has a 96-bit unique ID too, however, nothing is mentioned about wafer or lot ...

Resolved! Enabling and disabling CCR interrupts on a running timer.

Hello all. I am trying to set up a continuously running timer to use to set of interrupts at specific counts of the timer. So the user of this thing would say "setAlarm(n)" and at timer=n an interrupt goes off. But I also want interrupts for the ccr...

JSven.9 by Associate II
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Hello everyone I'm a RT embedded engineer and I want to ask question about HardFault_Handler debug. I'm working on STM32G070RB, Can somebody have a good tequinqe how debug HardFault_Handler?

void HardFault_Handler(void){ /* USER CODE BEGIN HardFault_IRQn 0 */  __asm volatile  (    " tst lr, #4                        \n"    " ite eq                          \n"    " mrseq r0, msp                       \n"    " mrsne r0, psp               ...

gilramon by Associate II
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