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Multi channel ADC + SPI + I2C

I'm using STM32 NUCLEOH743ZI2 board were I have written a code which consist of Multi channel ADC using DMA with timer, SPI and I2C protocols. SPI and I2C is not working whenever multi channel ADC is enabled else SPI and I2C is working fine. We are u...

GHARI.1 by Associate II
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Resolved! F411 System Clock Configuration with Internal Clock

I have been working F411RE Nucleo board with LL library for quite some time. I found the sample code for SystemClock_Config uses external oscillator as showed below. I wonder if there is any sample for internal oscillator. /* Enable HSE oscillator *...

HDaji.1 by Senior
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  • 3 replies
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Creating a non cacheable area of RAM on STM32H7A (B)

Using the linker script - How would I assign an area of AXI SRAM1 that is not cacheable by DCache? I am currently having problems with DMA transfers to the PWM peripheral when DCache is enabled (I think this is because I am sending 8bits to the HAL_T...

Trusted Firmware-M for STM32U5 or STM32L5

Hello,has anyone run TF-M successfully on STM32U5 or STM32L5 ? Does ST provide examples for this? I have NUCLEO-L552ZE and NUCLEO-U575ZI board.Looking forward to your reply!​

李放.1 by Associate II
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  • 2 replies
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Data storage on cloud using STWINKT1B

I know that there are firmware files to store data on sd card but i just wanted to know if there is a way to store raw sensor data on the cloud directly using the board?

RMhap.1 by Associate II
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How to solve HardFault or MemManage Handler for STM32H743?

Hello,I have implemented some source code on my original borad with STM32H743.(ex. use HAL_UART_DMA, HAL_SAI_DMA, and more.)I run without Breakpoint, but HardFault occurs.However, I run with Breakpoint, HardFault does not occur.According to the Fault...

Mapyam by Associate II
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  • 2 replies
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How Segger J-FLASH configures its external loaders?

A customer has a board with STM32F746 and QSPI flash.The board looks as derived from STM32746G-DISCO, though I'm not 100% sure.Their program has data in the QSPI flash, and they flash the app using J-LINK and Segger J-Flash.​Now, I cannot figure out ...

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Pavel A. by Super User
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Why does MemManage Fault occur in ITCM?

Hi,​​MemManage Fault occured in ITCM when I changed the system clock and DMA channel.Does ITCM cause errors? What are the causes of errors? Any ideas?​I changed below:system clock: 480MHz→400MHzDMA: DMA2_Stream1 →BDMA_channel0

0693W00000QMuYHQA1.png 0693W00000QMuYRQA1.png
Mapyam by Associate II
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  • 3 replies
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