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Hi,I have 2GB emmc on SDMMC1 bus.I wish to have first 1GB (0~1GB) as application code area and the rest 1GB(1GB~1GB) as FAT file system that access by user as USB MSC. Even more, the first 1GB i wish to have 2 partitions(like A-B bank) for fail safe ...
I'm using a Nucleo-F446RE board and have successfully flashed my application code to Sector 5 of the internal flash memory. The code runs correctly right after flashing, but it does not run after a reset or power cycle. It seems the MCU still boots f...
最近项目需求更改，原来的STM32F405RG换成STM32F413RG，其他外设均调正常，只有CAN不能工作（只使用到CAN1）。请问除了以下差异之外还需要调整哪里？
I am working on FDCAN communication using an STM32G0B1CCT6 microcontroller. I am trying to perform a simple Tx/Rx loopback test (and later communication with external tools like Vehicle Spy), but I am facing the following problem: FDCAN is not trans...
I have purchased STM32F103c8t6 microcontrollers from three different vendors, but they are behaving differently.I am working on CAN, and on the microcontrollers from one vendor, it is working properly. But on the microcontrollers from other two vendo...
Hello, I am currently in the midst of developing a super simple system to create a varying load. It's basically to resistors in series with a transistor in parallel of the second resistor. The transistor is driven by a PWM signal to bypass the secon...
Hello all, i got a firmware configuration problem, basically im using USB in FS modem and when i plug in the usb to the pc what happens is that sometimes it can be recognized and i see a network disk called ''boot'' but most of times it cant be reco...
Hi, I found a pretty interesting issue while developing an STM32H7 Series MCU.And I tried many things to figure out the cause but failed. T^T If you have experienced similar symptoms or know anything about them, I hope we can discuss it together here...
All control signals seem to be good: `DEN`, `VSYNC`, `HSYNC`, `CLK`. but pixel signals (R0 ~ R7, G0 ~ G7, B0 ~ B7) are always low. 1) DEN. 2) HSYNC. 3) VSYNC. 4) CLKalthough control signals correctly work, no pixel data lanes do not. Code that genera...
Hi,The STM32H7RSxx TRM specifies, for ETH_MACMDIOAR, the following CSR values: Bits 11:8 CR[3:0]: CSR Clock RangeThe CSR Clock Range selection determines the frequency of the MDC clock according tothe CSR clock frequency (eth_hclk):0000: MDC clock ...
