STM32 MCUs Products

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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Resolved! STM32F429 TIM1 trigger flag (TIF) issue

I have TIM1 configured in one pulse mode triggered by rising edge on TIM1_CH1 to generate single pulse. Timer works correctly (generate single pulse for each rising edge on input). Datasheet claims that TIF flag is set on trigger event in all modes b...

how iadd .o file link in ld file ?

i'm using stm32H7,i want to use ITCM/DTCM ram,so i want add .o file in stm32H7XXXXX.ld filei try .main_section { . = ALIGN(4); CORE/src/main.o(.data); . =ALIGN(4)}>ITCMRAM​​but gcc report errorso i want to known how fix it​?

Hhaon.1 by Associate II
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  • 3 replies
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How to use DMA control GPIO in STM32H750 series?

OK, I am using STM32H750BV, I have a driver that needs very critical timing control, so I want to use DMA trigger by timer, transfer memory data to GPIO BSRR register, let GPIO can according to time pass to generate the signal, but most of all refe...

EHD by Associate II
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  • 2 replies
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ADC values are not stable in STM32H723ZG

Hello everyone,With respect to the Subject I am facing problem in reading analog voltage across the analog pins in the controller specified.Following are the ADC configuration.1. ADC resolution = 12Bit2. Sclk = 256MHz3. ADC clock source = Sclk/44...

Arrhenius by Associate III
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  • 5 replies
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H723ZG Nucleo ADC clock/noise question

After assembling the X3 external 25MHz crystal and 2 caps and generating initialize code for 550MHz clock with CubeMX my NUCLEO-H723ZG board runs fine, except ADC. It is very noisy. The CubeMX configured the clock for ADC = 96.000671 MHz (PLL2P). In ...

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Louie88 by Associate III
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  • 13 replies
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STM32L071RB RX Halt Issues

Hi, We have been experiencing severe issues with RX UART on STM32L071.The RX bus stops receiving data while running, and the only way we could recover from it was to initiate the UART back again which probably clears the registers.Is anyone familiar ...

Wich is the STM32F429 PLLN maximum frequency?

User' manual says that the maximum PLLN or VCO output frequency should be between 100 and 432 MHz (pg. 227). However, I was trying to set the PLL clock and the SysClock to 180 MHz and also respect the 48 MHz clocks.One possible solution is to set the...

TCabr.1 by Associate II
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  • 10 replies
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