STM32 MCUs Products

About the calibration of the ADC on STM32H747

I am currently trying on the linearity calibration and I am following the protocol (down below) but I do not understand where I am supposed to get the saved linearity correction factor bits[159:150] (step 3)? Every single ADC register is 32 bits at m...

STM32F412R HSI clock calibration with LSE

Hello,I'm looking for a way to calibrate HSI by using LSE. I've found some documents that describes the way. My situation is a little bit tough. I can't change PCB and I can't draw a way from LSE to TIM5 - channel 4. I'm looking for a way which will ...

I use STM32H735 and her backup memory at 0x3880_0000 (4KB). All works OK if I use SCB_CleanDCache_by_Addr(0x38800000, 4096) after a write. Is it possible to disable dcache in this area ?

I tried to configure MPU using standard configuration generated.I tried this codeMPU_Region_InitTypeDef MPU_InitStruct;   HAL_MPU_Disable();   /* Configure the MPU as Strongly ordered for not defined regions */ MPU_InitStruct.Enable = MPU_REGION_ENAB...

I Have a source code written with C++ Math Calculation(.cpp + .h files). I can run it on desktop by compilling .dll/ .exe or .OS. Is there any chance to compile or run this code on STM32F4 Discovery Board. What should ı have to do?

SCK Active during CS High

I'm making use of the STM32L433 and using SPI to communicate with a LLCC68 from Semtech.I've noticed that my SCK is active after my CS goes high.Is this normal behavior?Code Snippet for SPI Write:LLCC68_StatusTypeDef spiWrite(uint8_t* data, uint8_t s...

Bug in STM32CubeIDE, Version: 1.10.1, Build: 12716_20220707_0928 (UTC), regarding IRQ on DMA transfers with STM32F401

I have a small project which should generate an interrupt whenever a DMA transfer has completed. If I build the code for an STM32F411 then it works exactly as expected. If I build that same code for an STM32F401, which is within the same family as ...

Hi There, I have the SMBUS example code for STM32L4R5ZI-Nucleo. As per the spec this code should be fully compatible with STM32L496z-Nucleo. However, when I flash the example FW from STM32L4R to STM32L496 the SMBUS functionality does not work.

STM32F070 Standby Mode (Not waking up...)

I wanted to test the wakup pin on the stm32f070f6.I have set pin PA0 to SYS_WAKUP1 and gave it the user name "WAKE". Before the user while loop I call: HAL_PWR_EnableWakeUpPin(WAKE_Pin); HAL_PWR_EnterSTANDBYMode();To enable wakeup (I thought) and put...

STM32H723 FDCAN1 AT CLASSIC MODE Not Working

FDCAN1 Settings:FDCAN_FRAME_CLASSIC;FDCAN_MODE_NORMAL;FDCAN_EXTENDED_ID;FDCAN_FILTER_MASK;TX/RX FIFO Enabled.Call Functions In sequency:MX_FDCAN1_Init(); hfdcan1.Init.NominalPrescaler = 5; hfdcan1.Init.NominalSyncJumpWidth = 3; hfdcan1.Init.NominalTi...

The match interrupt on LPTIMx->CCRx is triggered when LPTIMx->CNT > LPTIM->CCRx - not on equal (=) as one might expect

On the STM32U5xx, ST decided to keep this interpretation of "match". It is present on other chips as well, see https://community.st.com/s/question/0D53W000004J0srSAC/stm32l0-lptim-generating-random-compare-match-interrupt-when-changing-compare-match-...