Bugs in STM32G4, RM0440 Rev 7 for FDCAN:1)STM32G4, RM0440 Rev 7  44.3.3 Message RAM.It is written on the page 1953:"In case of multiple instances the RAM start address for the FDCANn is computed by endaddress + 4 of FDCANn-1, and the FDCANn end addre...

RM0440 Rev 7 (STM32G4), 39.5.12 NSS pulse mode.It is written on the page 1753: “This mode is activated by the NSSP bit in the SPIx_CR2 register and it takes effect only if the SPI interface is configured as Motorola SPI master (FRF=0) with capture on...