STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...
Hi there,I use backup SRAM and RTC in STM32F407. I have a diode between VDD and VBAT and 2.2u capacitors connected to VCAP_1 and VCAP_2. 3v CR1220 battery is connected to VBAT. Now the issue is that SRAM data are wiped when VDD power is off and batte...
We are migrating from STM32F103 to STM32L4. The code architecture is the same, as the product basically is the same. We just upgrade the micro. We have an SPI that is configured in slave mode, and a device that supplies clock to the SPI. DMA is u...
NUCLEO-F446RE board has 2 MCU. One is on the upper side(STM32F103CBT6) and the other one is on the downside (STM32F446RET6U). When we burn the firmware code, the code comes from DP/DM and goes to the upper one(STM32F103CBT6). Afterward, the upper one...
I am using STM32F411VE for testing I2C driver, in which i have defined 9 test cases using HAL_Mem_read, HAL_Mem_write, HAL_Master_transmit and HAL_Master_Receive(inblocking and non blcking mode(IT, DMA)). I have defined each test cases as a function...
We are migrating project from F303 to G473, but the ADC output of G473 confused us with a strange problem, and with same circuit with F303 project below:sampling time: 66nssampling period: 1.16usvoltage range: 1~3VVdda / Vref: 3.3VHere is thre proble...
Good day everyone.Trying to make SAI work in TDM mode with DMA on STM32F746.Need to transmit 8 stereo channels, the sample is 16-bit long. So 16 * 2 * 8 = 256 bit frame.Init code: hsai_BlockA1.Instance = SAI2_Block_A; hsai_BlockA1.Init.Protocol = S...
I`m working with STM32G0 and SPI in slave mode.Is it possible to clear TX FIFO buffer without any master`s clock?In HAL library there is a function called "HAL_SPIEx_FlushRxFIFO", but no method to clear TX FIFO,
