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I am trying to read several adc channels on the stm32 microcontroller, but it won't let me, it only reads the first one. I have seen in the registers that when changing channel what it does is that it sets the selected channel bit to 1 and does not m...
Hi I am using an STM32G071 Nucleo board and would like to know if it is possible to achieve the advertised current of 40nA in shutdown mode.I have no problems entering shutdown mode but the observed current with my nRF PPK2 is closer to 1uA. I have d...
we use the timer capture for Hall inputs. we were able to program the XOR input using the filter and can geneate an interrupt, but I also want to read the individual inputs using the filter.feature. When I read the corresponding IDR it seems it is ...
Hello,I use the internal DAC of the processor. Even the initial value of the DACs are equal, I got 1V out from the first output of the DAC, and 2V output from the other DAC output. Why is that happen?/* USER CODE BEGIN PV */ // DAC Settings float...
I've been doing the majority of my FDCAN development with 1 or 2 nodes.Recently, I have expanded my "network" to 7 nodes. 4 of these nodes send data at the same time.(I mean, 1 second intervals from power up. They are all powered simultaneously)With ...
Anybody noticed?https://www.st.com/content/st_com/en/stm32-mcu-product-selector.htmlFor what it's worth. After oh so many years.JW@Lina DABASINSKAITE , this is example of information which would need to come from ST here, regularly. This is what wou...
Currently, I am seeing no signals on the SCLK and MISO/MOSI lines on the SPI4 lines from a STM32F427 chip to a SPI flash during an attempted read/write. At the moment, I've done the following:Enable GPIO clock (HB1) and SPI clock (PB2)Configure CS:pi...
Any chance STM32 MCUs will adopt native i3c support any time soon? Many new devices, including some from ST (like the LPS22HH), support it. It's a compelling (new-ish) standard.
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Hi allI'm trying to distinguish between the interrupt sources in the NMI handler on a STM32G031 - particularly the RAM parity error.I have everything in place and I can provoke a parity error. The NMI ISR is called as expected, but if the SYSCFG_CFGR...
