The new STM32H7R/S lines are built on the success of the STM32H7 series, offering even higher performance and security at a lower cost. The STM32H7R/S is a bootflash-based MCU powered by a Cortex®-M7 core running up to 600 MHz, with 64 KB of user fla...
I'm building a micropython firmware for running tensorflow lite for microcontroller examples. One of the main reference examples is called micro_speech and involves reading audio from a MEMS microphone at 16Khz using DMA and I2S and then feeding it ...
Hello,there seems to be a problem in function SD_read with reading data in DMA transfer mode to cached buffers.I've enabled cache handling with#define ENABLE_SD_DMA_CACHE_MAINTENANCE 1but there is a serious problem with calling SCB_InvalidateDCache_b...
/*CODE to generate PWM signal of 50%*/#include "stm32l476xx.h"#include "pwm.h"void pwm_init(void){ /*RCC configuration*/ RCC->AHB2ENR|=RCC_AHB2ENR_GPIOEEN;//ENABLE GPIOE RCC->APB2ENR|=RCC_APB2ENR_TIM1EN;// ENABLE CLOCK ACCESS TO TIM1 //RCC->APB1ENR1|...
Hello,I'm working on 2 NUCLEO-F767ZI Demo Board.I'm using STM32CubeMX with last firmware package to generate the code and STM32CubeIDE to modify it and debug it.One of the board is used as an I2C Master, the other as I2C Slave. Every thing work fine ...
Here is my code in main() to config field NRST_MODE: HAL_FLASH_Unlock(); HAL_FLASH_OB_Unlock(); gFlashOBST.OptionType = OPTIONBYTE_USER; gFlashOBST.USERType = OB_USER_NRST_MODE; gFlashOBST.USERConfig = FLASH_OPTR_NRST_MODE_1; HAL_FLASHEx_OBProgram(&...
I was finally able to find the correct settings to configure my CAN peripherals with correct bitrate after tweaking for a while in STM32CubeMX. The settings that work do not make sense. FDCAN2 is 4 times slower so I had to make clock divider for FDCA...
Hi everyone, I'm just trying to test and verify some clock frequencies for a PWM waveform are correct. I used CubeMX to generate some code that has set the clock frequency of the MCU to 72 mHz and I am trying to achieve a 20 kHz PWM frequency. I enab...
As per RM0468, STM32H72x and STM32H73x chips have 192 KB of SRAM in the D1 domain that is 'sharable' between ITCM and AXI SRAM, ie. it can be allocated as ITCM or AXI SRAM with 64KB granularity,It is known that SRAMs in D1 (or any other domain for th...