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Hello,I am using NUCLEO-F756ZG. My application is ADC related. I am measuring an analog signal at high sampling rate. Recently, I had a discussion with my team and had an interesting proposal. Our target signal is pretty much guranteed to be within 0...
On STM32G474, I have a loop where I read ADC values, process them, and write the result to DAC.I am using the dual ADC mode and reading ADC12_COMMON->CDR . I do not care if I read the previous conversion result, in this case, is there a reason to che...
Hello, I am having a confusion in understanding the Clock Frequencies for STM32L452RE. In the Datasheet its mentioned that "Several prescalers permit to configure the AHB frequency, the high speed APB (APB2) andthe low speed APB (APB1) domains" It al...
I'm working on migrating a design from STM32F405 series to STM32G473 series, both LQFP100 package, both use FSMC for access to external SRAM (in multiplexed mode; I have separate address latches clocked from FMC_NADV capturing A0..A15 from D0..D15.) ...
In my project, my MCU (F411) uses I2C HAL API routinely to read from a sensor device.When some event happens, my interrupt handler will use I2C API to read from different register from that device; so my question is:Is HAL API thread safe? Although I...
I've been having issues with getting an SD card working on an STM32L4R5ZI Nucleo board when using essentially the same code (with minor tweaks) without issues on the STM32WB55 Nucleo board. I've been going through the code of both to determine where...
I have previously used the STM32F103C8T6 is a number of projects and was considering switching to the STM32H503RBT6. My use case is low volume R&D work. With the F1, I would use JTAG for programming but the option isn't available for the H5 in CubeMX...
Hello,I am using an stm32h750. I have an ADC group that includes 4 inputs from GPIO ports and the 3 internal ADCs (VBAT, CPU Temp, Reference Voltage). It's set up with DMA. The conversions run at 150hz.We use a coincell battery voltage as input to VB...
Hi,I have an issue with the CAN1 controller in my MCU. I have connected the CAN transceiver to PA12(TX) and PA11(RX). When connected to the CAN Bus I can see the frames coming to the MCU(RX line) and the ACK bits are visible on the TX line. Unfortuna...
tl;dr: accessing external memory over debugger results in additional unwanted write accesses to adjacent memory locationsI have an FPGA that is accessed via FMC over a 16-bit async connection (16-bit data +15-bit address), sort of like an external SR...
