Ask questions, find answers, and share insights on STM32 products and their technical features.
Hi all,I'm trying to find out if any STM32 MCUs support hardware input qualification on GPIOs, similar to what's available on TI C2000 MCUs.On the C2000 series, GPIOs can be configured for input qualification using a sampling window—typically 3 or 6 ...
Hi, I have configured my STM32H563AI CubeMX-project to use "JTAG with Trace Synchro(4bits)" and assigned the corresponding pins. Also, I explicitly activated the corresponding registers in DBGMCU and DCB by adding: SET_BIT(DBGMCU->CR, DBGMCU_CR_TRA...
What is the process to use the ADC on STM32L152rct6 to wake up the micro from Sleep?
Hey everyone,I'm currently working with the STM32H7S78-DK.I'm trying to set up an external memory loader project, executing code from external memory with XIP, while also partitioning out the SDRAM in a few different addressable chunks in the memory ...
Hi,while I'm configuring the FMC interface i come cross this memory map and i couldn't understand it. Does the FMC SDRAM Bank 1 have 4 possible regions? if yes, does SDRAM Bank 2 have the same option.what about the External Memory region, are those f...
I am confused about which clock(s) drive the timers. In the reference manual is says the APB clock drives the timers but there are 5 APB clocks. Also, in STM32CubeMX there is a "Timer Group Clocks". What clocks drive which timers or is the one dri...
I have questions on the System Memory Boot Mode of the STM32G070CB MCUSetup:Access the System Memory Bootloader Mode every power cycle. Hence, I updated the Option Bytes as below:The MCU contains the Application image only; it does not contain a cust...
I am trying to detect both rising and falling edges on a GPIO input using EXTI.I am using a STM32H755 (144 pin) - SYSCLK is 400MHz, but I am using the CM4 core, so the CPU clock is 200MHz. APB Timer clock is also 200MHz.The signal I am monitoring is ...
How to unbrick a C0 if user firmware reprograms SWD pins as IO? Because by default BOOT0 pin is disabled so there's no way to enter the bootloader unless it's enabled in OPTIONS bytes. I've added a failsafe 2 second delay at bootup before running any...
Whether the two buses can be used at the same time？ Winbond's SDRAM is used to find a high probability of reading and writing errors in SDRAM data。 but there is no problem with using ISSI. If you don't read or write to the external SRAM, it's fine。
