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Hi Friends,In STM32H7 MCU, both M7 and M4 can access shared memory, such as D3 SRAM4. I am going to use a D3 SRAM4 address as a place to share some status information between M7 and M4. If a 32bits word is defined shown as below, can the access from...
The reference manual RM0503 rev2 has inconsistent information about the flash wait states.Table 9 in §3.3.4 shows three options: 0WS, 1WS, 2WS (and, by the way, it says that all three of them correspond to "1 CPU cycle", which seems wrong).Instead, §...
I have a custom board with a STMWB55 (master) and a STM32F031 (slave). They communicate over SPI using DMA. Unforturenately there are communication problems. In order to identify the problem I have simplified the setup. I have used a ST NUCLEO-F031...
I am using STM32G474VET3 controller.As i am using DAC out voltage for my application.So i want to know the DAC output stability, performance over temperature, & the temperature drift at Maximum junction temperature 150 °C.Also any other factors affe...
This question is about HAL_SPI_TransmitReceive.If a slave starts sending 8 bytes of data after the 4th byte sent by the master, is it possible to use HAL_SPI_TransmitReceive without a dummy (ignore) buffer?We will be the master side.Our assumption is...
Hi,I use STM32U575.The STM32U575 works as a USB CDC ACM device and I implemented it in standalone mode.OTG_FS_IRQHandler is called when data is received from the host device.Is there a way to determine that when OTG_FS_IRQHandler is called, it is due...
Posted on July 28, 2016 at 07:53Hi,We are developing a display using STM32F439NIH6 Microcontroller in our design. We have the following technical queries:We have referred to your evaluation board design and we are interfacing STM32F439NIH6 with SDR...
Hi there! I was hoping that the H5 series would be like a faster U5 series but instead they seem to be very cut down in terms of features. i.e. the H5 looks like a faster crippled U5.The U5 has graphics accelleration and HS USB but the H5 has neither...
* In the reference manual RM0503 rev2, in §5.4.4 (description of RCC_PLLCFGR), the description of PLLR[2:0] indicates:Caution: The software must set this bitfield so as not to exceed 54 MHz on this clock.* In the reference manual RM0503 rev2, in §5.2...
Hi all,i am using STM32C011F4U6 and i want communication between Uart1 _baud rate -115200 _8N1 and Uart2_Baud rate _4800_7E1.But STM32C0 haven't 7 bit communication option. How can i do this?Thank you
