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BarryWhit
Lead II
since ‎2024-04-11

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  • 568 Posts
  • 24 Solutions
  • 96 Kudos given
  • 204 Kudos received

User Activity

STM32H745: DS and RM misalignment: doc update required

2024-09-03
@Amel NASRI (Update: Comment moved here from STM32H745: DS and RM disagree, which to believe?) I've also verified that these errors still exist (though table/page numbers have changed) in latest docs ("DS12923 Rev 2 March 2023" and "RM0399 Rev 4 June...

Correction Request: AN2867 Oscillator design

2024-08-18
Rev 19 Page 16/59:I believe this should read "increase" instead. The purpose of Rext is to limit the current and thus lower power dissipation in the crystal. So, lowering Rext increases power dissipation. A separate issue is that this phrase is awkwa...

Bug: CubeMX should warn H7 users against PC2_C/PC3_C pitfalls

2024-08-14
Dear ST, Users have for years been complaining that Cube is not giving them fair warning regarding speed limitations of PC2_C/PC3_C in STM32H7. Customers are having to respin boards because they fail to notice the fine-print in a 300 pages datasheet....

Attached: Spreadsheet of STM32 appnotes and the Knowledge base with date/title/url

2024-08-11
I was going to submit a forum feature request to add an "Insert Appnote Link" button to the editor with filtering capability to save members some time when answering question. I immediately realized that will never happen.Then I realized that while I...

Bug: STM32G4 Clock configuration panel bugs with HCLK at 170Mhz

2024-08-07
Several issues here.First issue, the indicated limits on PLLR are wrong:The error suggests the PLL output can be no higher than 150Mhz, which is wrong since the chip supports HCLK freqs up to 170Mhz. Which is also explicitly stated below the HCLK box...
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