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Posted on November 30, 2017 at 12:35MCU: STM32F777IIHow can I use the backup SRAM to store non volatile data? Are there any examples?Is there also way to let the compiler know that this is the area of RAM to use for allocating these variable which I...
Posted on November 29, 2017 at 13:57With the community's help I have code that runs and demonstrates interrupts and interrupt handling. I need more information to understand how the STM32F3 series parts process event changes (interrupts) such as the...
Posted on September 29, 2017 at 14:32Hello,I am using STM32F446 MCU. ADC chnanel 10 & ADC channel 12.ADC ref voltage is 3.0V.I am getting 0 count for 0v on ADC channel 10.But I get ADC count value 87 for ADC channel 12. which calculates to 1 V.what ...
Posted on November 29, 2017 at 12:04Hello,I am using a STM32F429ZIT Discovery board and It is working properly when I using some timers (TIM1, TIM2, TIM3, TIM5 and TIM5) with its interruptions, also using SPI - DMA and ADC functionality.I have added...
Posted on November 26, 2017 at 06:27 Dear Community, I'm new to programming and STM32 microconrollers, though, I have to perform FFT of 50Hz voltage. Well, after defining my core by ARM_MATH_CM7 in arm_math.h, I get error messages like: ...
Posted on February 24, 2015 at 10:50 The original post was too long to process during our migration. Please click on the attachment to read the original post.
Posted on September 28, 2017 at 10:00Using CubeMX with CubeL4 1.9.0, I have the following problem.I'm using FreeRTOS with tasks defined as either weak, or external (weak is only used because the default task cannot be external for whatever reason). ...
Posted on September 02, 2014 at 10:40There appears to be a bug in the HAL drivers for the RTC. I have only recently migrated to STM micros and am in the process of rewriting a number of projects to use them. I have a project running on a STM32F405R...
Posted on November 29, 2017 at 22:47Hi, I have a nucleo f401re board and a x-nucleo-cca01m1 shield mounting STA350BW IC. Nucleo transmits data as a master to the shield using I2S half duplex communication. I want to know what is Master Clock's purpo...
Posted on November 27, 2017 at 11:15Dear All,I have some questions concerning the cache of the cortex M7 & H7 micro controller.I use an external SDRAM and the data and instruction caches are activated. Now, if I define the region as 'shareable', I l...
