M7 and H7 cache (sharable performance)

Dear All,

I have some questions concerning the cache of the cortex M7 & H7 micro controller.

I use an external SDRAM and the data and instruction caches are activated. Now, if I define the region as 'shareable', I lose a factor 3 in the system performance (just like if the cache is not activated). Any experience on it? Here is my MPU initialization.

Sharable ... but bad performances

static void _MPU_Configuration(void) {

      MPU->CTRL = 0x00000000; // Disable the MPU

// Attributes for the SDRAM area (0xD0000000)

      MPU->RNR = 0x00000000;      // Region 0

      MPU->RBAR = 0xD0000000;     // Address

      MPU->RASR = (0<<28)         // XN: 0 executable

               | (3<<24)         // AP: 11 read-write

               | (0<<19)         // TEX: 000 normal

               | (1<<18)         // S: 1 shareable

               | (1<<17)         // C: 1 cashable

               | (0<<16)         // B: 0 non bufferable

               | (0<<8)          // Sub-region disable

               | (22<<1)         // 8-MB

               | (1<<0);         // Region enabled

      MPU->CTRL = (1<<2)          // Enable the usage of all the default map

               | (1<<1)          // MPU is enabled during the fault

               | (1<<0);         // MPU enabled

      MEMO_SYNC_BARRIER;

      DATA_SYNC_BARRIER;

      INST_SYNC_BARRIER;

// Enable branch prediction

// Normally not necessary (always on)

      SCB->CCR |= (1<<18);

      DATA_SYNC_BARRIER;

}

Non sharable ... and great performances

static void _MPU_Configuration(void) {

      MPU->CTRL = 0x00000000; // Disable the MPU

// Attributes for the SDRAM area (0xD0000000)

      MPU->RNR = 0x00000000;      // Region 0

      MPU->RBAR = 0xD0000000;     // Address

      MPU->RASR = (0<<28)         // XN: 0 executable

               | (3<<24)         // AP: 11 read-write

               | (0<<19)         // TEX: 000 normal

               | (0<<18)         // S: 0 non shareable

               | (1<<17)         // C: 1 cashable

               | (0<<16)         // B: 0 non bufferable

               | (0<<8)          // Sub-region disable

               | (22<<1)         // 8-MB

               | (1<<0);         // Region enabled

      MPU->CTRL = (1<<2)          // Enable the usage of all the default map

               | (1<<1)          // MPU is enabled during the fault

               | (1<<0);         // MPU enabled

      MEMO_SYNC_BARRIER;

      DATA_SYNC_BARRIER;

      INST_SYNC_BARRIER;

// Enable branch prediction

// Normally not necessary (always on)

      SCB->CCR |= (1<<18);

      DATA_SYNC_BARRIER;

}

Thank you for your advises,

Best regards

   Edo.