Ask questions, find answers, and share insights on STM32 products and their technical features.
Posted on March 05, 2018 at 13:31 Hi, i want to send only 1 Pulse and i thought to use a timer. I use the Board B-L475 iot and i want to generate the pulse on TIM2_ch3 (PA2). I had build the HAL with stm32cubemx. Before the while(1) b...
Posted on March 01, 2018 at 15:13migrate Compiler 5 -> Compiler 6 in KEIL MDK. https://www.youtube.com/watch?v=rt6tD0ffYIk&index=2&list=PLgfqWPj3VNU-5luCbv1Y-gutHx7aNXb9p&t=0sI am using STM32F1 DFP, I install the latest one. It seems don't work with...
Posted on March 04, 2018 at 09:21hiI have this project that there is a gate that allots of the car go through it one at the time. I need RFID Chip that can detect passive tag with a range of 10 meters or longer for detecting those car passive tag an...
Posted on March 02, 2018 at 11:49For both USB OTG FS and HS controller the CIDSTS bit in the GOTGCTL register does not reflect the status of the USB port. When pulling the ID line low or leaving it in floating state the register value changes, but C...
Posted on March 05, 2018 at 08:38hi,My Question is this:we used a RTC chip, which part number is M41ST85WMH6,and a M4T32-BR12SH be used on top of it.when we supplied the power to it from its VCC pin(pin 28),the time is operating in normal mode,but w...
Posted on January 17, 2018 at 11:30The STM32F4 has 4 Kbytes of backup SRAM.They seems not to be accesable at a certain adressThe HAL lib has also a driver for it. But the functions are not enabled default. The library stm32f4xx_hal_sram is needed fo...
Posted on March 05, 2018 at 05:29In Section 3.5.1 of the STM32F031 datasheet states:�The VDDA voltage level must be always greater or equal to the VDD voltage level and must be established first.�The statement �VDD voltage level and must be establis...
Posted on March 05, 2018 at 05:28Does ST have support for programmable logic in their micro-controller portfolio (like http://www.cypress.com/products/psoc-5 or http://www.microchip.com/design-centers/8-bit/peripherals/core-independent/configurable-...
Posted on December 16, 2017 at 22:38The Dual bank mechanism works by switching internal flash banks while code address stays the same. How to extend this mechanism to two external QSPI flashes operating in XIP mode? Is gating QSPI chip select using ...
Posted on January 24, 2018 at 21:07Should be MCKDIV.Also, the same typo is in the relevant .svd files, making thus MCJDIV appear as xCR1 bitfield name in debuggers (spotted in https://community.st.com/thread/46652-f446-documentation-saispdif-tx-bit-...
