STM32 MCUs Products

STM32L4 Nucleo LSE drift

Posted on May 07, 2018 at 21:40Hi all,is there a way to improve LSE drift on L4 Nucleo board? Or all I can do is to migrate to another crystal with higher precision?Thanks, and regardsjerry

Resolved! RS485 frame reception through DMA and UART

Posted on April 17, 2018 at 15:34HelloI am starting a new project in which I have to use a RS4785 communication and this time, I'd like to do it well.The problem is the following:If I want to receive a frame with UART using DMA, I need to call HAL_...

Data Block CRC failure (DCRCFAIL) when using SDIO with DMA

Posted on February 10, 2017 at 10:40I am getting Data Block CRC failure (DCRCFAIL) when I configure data transfer in SDIO using DMA.I am not using HW Flow control in SDIOThe same code works fine without DMAWhat is the reason for CRC failure and any ...

How to stop regular convertion on STM32F4 ADC in continuous scan mode

Posted on May 09, 2018 at 00:03Is it possible to stop the regular conversion in continuous scan mode (on STM32F437) and start from the beginning without disabling the ADC (to not affect the injected channels conversion )? I.e. when all required samp...

STM32F429 WFI w/ interrupt disabled

Posted on February 07, 2018 at 09:47Hi,I'm developing on a custom board with STM32F429. I need to use stop mode for power consumption. We have some external interrupt (e.g. interrupt from accelerometer) we use to wakeup from stop mode.Wake up is wor...

STM32H7: How can trace/diagnose stack overflow using STM AC6 Workbench ?

Posted on April 30, 2018 at 06:19Hi All,Recently, I am stucked in an issue where if i use 'printf('%f', num)' ( where num is float type) then system gives 'hard fault' but if i use 'printf('%d', num) ( where num is integer) then system works fine.I ...

STM32F767 ART versus ICache

Posted on May 08, 2018 at 15:37I'm using an STM32F767 at 216 MHz with LL_FLASH_LATENCY_7. The IDE is Keil with IROM (Flash) at 0x8000000. STM documentation AN4667 says, 'Flash memory is accessible by the CPU through ITCM starting from the address 0x...

Get Read out protection is activated from the STM32 ST-Link utility on the STM32L4R9i-DISCO

Posted on May 09, 2018 at 05:39Hi , I have one of STM32L4R9i-DISCO MB , I try to set system clock 120MHZ(MSI ON & PLL ON) , HCLK 15MHZ. When MB to running the system clock initial function after then the MB to connect with STM32 ST-Link utility , Th...

DAP access to SRAM

Posted on May 08, 2018 at 22:52Hi -Is it possible for a debugger to directly r/w to embedded SRAM via one of the debug APs (access ports) on the ♯ That is, I don't want to access SRAM via the M7 since the &sharpcache might be enabled. I'd like to ...

STM32F415RG exit from standby without reasons

Posted on May 09, 2018 at 02:11HI, i have a project for stm32f415rgt, i generated the code with mxcube (last version) but i have a strange behaviour.I setted the ALARM_A + ALARM_B + Tamper + PA0PIN to exit from stnadby, but every 3300 seconds, the m...

STM32 MCUs Products

Forum Posts

STM32L4 Nucleo LSE drift

Resolved! RS485 frame reception through DMA and UART

Data Block CRC failure (DCRCFAIL) when using SDIO with DMA

How to stop regular convertion on STM32F4 ADC in continuous scan mode

STM32F429 WFI w/ interrupt disabled

STM32H7: How can trace/diagnose stack overflow using STM AC6 Workbench ?

STM32F767 ART versus ICache

Get Read out protection is activated from the STM32 ST-Link utility on the STM32L4R9i-DISCO

DAP access to SRAM

STM32F415RG exit from standby without reasons

STM32G070 Fastest time for ADC continuous mode dat...

Disabling write protection fails on STM32F401RE

Artifact Filename based on a Fw costant

CAN filtering to hit all filters not first one

Initializing the HDP on STM32N6

[solved]STM32G RTC sets to some value afterr reset