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Posted on February 21, 2017 at 08:22hi,i write code to wake up with uart interrupt for stm32f4 discovery board.before sleep i use deinit uart function and configure rx pin as a gpio exti, in exti handler function i use deinit pin and init uart funct...
Hello everyone,For my current project I need the FreeRTOS+MPU to work on H7. I got it somehow to work with DTCMs. However, when I try to move the complete memory allocation to the AXI SRAMs the FreeRTOS is hanging in the systick handler (there is a f...
I am trying ti adjust the timer2 of the stm32f4 to 400khz but it does not work. Even though my calculations on Prescaler and counter are right for the frequency that i aim for, Timer is not working as it should be. By the way i am using Hal library.
Window10My installed STM32CubeMX 4.23.0 has been running fine, but today suddenly double clicked on the .exe file gave no response. What might had happened and any idea aside from reinstall it? Best,Brian
Hello,I tried to connect to the board P-NUCLEO-IOD01A1 with IO-link control tool but without success . I think that the mcu doesn't have the IO-link software.Could you please support me to connect and test the IO-link protocol.
Section 16.4.5 talks about the DMAMAX request generator but I cannot find a definition for what the SIG_ID bits mean.DMAMUX1_RGxCR and DMAMUX2_RGxCR reference SIG_ID but I couldn't find a definition of these bits.
Section 13.5.12 talks about TSEL[5:0] but I couldn't find the mapping for the Trigger Selection bits.
I would like use the DP83848 in RMII mode due to the number of available pins in the project.LwIP supports DP83848 with MII only and for RMII just the LAN8742A.The folllowing pins of DP83848 are not connected:RX_CLK, TX_CLK, RX_DV, COL, RXD_2, RXD_3,...
Posted on January 10, 2018 at 17:15Hi,In stm32f7xx_ll_adc.h, from revision 1.8 of HAL (stm32cube_fw_f7_v180.zip), the following register base addresses are defined:#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF07A4A)) #define TEMPSEN...
STM32G071RB: According to RM 3.7.1 reset value of FLASH_ACR is 0x00040600, verified on hardware. But the description of indiviual bits doesn't fit.RM: Bit 11 ICRST, Bit 10 reserved (cleared), Bit 9 ICEN, Bit 8 PRFTEN, so cache enabled, prefetch disab...
