Hi everyone.I'm trying to setup TIM2_CH4 remapped as input capture, in order to detect rising edges on PB11.I'm working with HALs. And my code is next:First of all, for initialization: // APB2 (which is 64 MHz) at 8 MHz timer_cap_timhandle_.Inst...
Hello,I use TrueSTUDIO 9.2.0 and I sometimes get the followingerror:warning: Remote failure reply: E31C:\Users\***\AppData\Local\Temp\truestudio8442355296883488729gdbscript:14: Error in sourced command file:Remote communication error. Target disconne...
Hello,I am using the stm32 F767ZI development board for a project. This is my first time using this board and only my second time working with an MCU in general. The software I am using is CubeMX and Attollic Truestudio.My current goal is to read dat...
Posted on March 26, 2018 at 20:32In CubeMX 4.25.0: Project -> Settings (or just Alt-P): shows Project and ToolchainFolder locations: But the project name get appended to these locations every time you enter the settings panel, so the co...
Hi all, I'm working on STM32L071CBTx. I'm trying to get external interrupt using GPIO pin in STOP MODE. I'm able to go to Stop Mode with RTC Enabled and also able to get the external Interrupt while in Stop Mode. But as per my requirement, I need a d...
Posted on June 19, 2018 at 14:13Hello everyone,I'm currently trying to get as accurate ADC values as possible from a STM32F072. I'm using the NUCLEO-F072RB and wanted to use the internal stored reference voltage value for calibration. But I'm alread...
Posted on December 17, 2015 at 10:06Hi,We are working on a design utilizing the STM32L151 MCU, which is to be programmed over a UART link using the internal bootloader. Selected baudrate for programming is 115200 (with even parity).The issue we are ...
I am trying to configure my stm32L4 device clock for 80MHz with PLL I am trying to understand a piece of code i found online could someone explain what the c code below meansRCC->PLLCFGR = (RCC->PLLCFGR & ~RCC_PLLCFGR_PLLN) | 20U << 8; RCC->PLLCFGR =...
WHEN TRY READ ADC WITH DMA DMA ERROR TRANSFER FLAG SET DMA STREM CHANLE DISABLE AUTOMATIC FOR SET DMA CORRECTLY MUST CERFUL ABOUT WHICH PARAMETER
Hello,I want to use ADC1 and 2 with close to maximum sampling frequency. Now I found on page 899 in RM0433 Rev5 a note that there will be a resynchronization between adc clk (using adc_ker_ck to achieve the highest possible clock) and AHB1 clk. I don...
