STM32 MCUs Products

Hi there, I'm looking for 3D Data of the NUCLEO-F401RE development board. Is it possible to get this info somewhere / somehow? Thanks Markus

I have a problem with configuration the TIM1-ETR in stm32f1

I want to use the external clock mode 2 but it dose not work ,configure the PA12 that connect to TIM1-ETR AND make push button pull down to send pulses to that pin(PA12) to detect high edge and make up count to the variable "upCount" in the code ,i t...

Problems reading correct data from AD7746 using STM32 I2C HAL library

I am trying to read capacitance and temperature from the AD7746 capacitance-to-digital converter, using STM32F103 and HAL I2C library (SDA and SCL pulled up with 2k and Vcc = 3.3 V). I did it before using AVR (using Codevision) and it worked fine, bu...

Use QSPI Nor Flash in MemoryMappedMode and FMC SDRAM at the same time

When i used a bootloader to make user program run from QSPI Nor Flash in MemoryMappedMode, it worked well.But now i want to run user program from FMC SDRAM.So firstly i plan to initialized both QSPI Nor Flash(MemoryMappedMode) and FMC SDRAM,then copy...

Best practice for application architecture (user input, screen updating, file writing)

Hi, my application needs to handle CAN message input, Updating the screen through UART, constant buffered LOG file writing to MicroSD card. I was wondering what kind of flow I could use?For CAN messages I could use interrupts and update variables (th...

How to translate this DMA configuration from a PSoC device to a STM32

The code below was implemented using a PsoC device. Maybe someone here can help me understand it and do the same in a STM32 device. AFAIK, the code is intended to build a quad buffer, but I don't understand how this is being implemented within a sin...

STM32H7 - Handling with 2 MPUs

Hello, the STM32H7 (dual core) has two dedicated memory protection units. If I configure one MPU to make a memory region only accessable as readonly, does the memory protection unit from the other core inherit those configuration or is it bypassing ...

Can anyone point me to "soft error" stats on the STM32L452 SRAM and Flash arrays? Lacking that, can anyone tell me what design rule/geometry the SRAM and Flash arrays use (in nm), from which I can estimate the stats?

STM32G4 ADC Errata

Hello,For STM32G4 Rev Y:Errata 2.7.3Wrong ADC result if conversion done late after calibration or previous conversion DescriptionThe result of an ADC conversion done more than 1 ms later than the previous ADC conversion or ADC calibration might be in...