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New possibilities for the ultra-low power segment!

STM32U0 is the first Cortex-M0+ with a static consumption of only 160 nA in standby mode with RTC (Real-Time Clock) and 16 nA in shutdown. It also achieves 118 points in CoreMark and targets SESIP level 3 and PSA level 1 focusing on firmware code pro...

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Hello, I am working on the stm32f373C8T6 MCU and trying to get some values out of the SDADC but I don't get any values apart from 0 and sometimes 5209/5217 for some reason. I am following the datasheet's instructions that I will display below.

Initialization 1. As prerequisite, fill in the HAL_SDADC_MspInit() :  Enable SDADCx clock interface with __SDADCx_CLK_ENABLE(). Configure SDADCx clock divider with HAL_RCCEx_PeriphCLKConfig. Enable power on SDADC with HAL_PWREx_EnableSDADC(). Enable ...

RKula.1 by Associate
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Regression from RDP level 1 to 0

Hello,I'm trying to test RDP levels configuration on STM32H753.Here is the code I've tested (on a Nucleo 743 with STM32CubeIDE):int main(void) { HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_USART3_UART_Init();   OBInit.Banks = F...

Gpeti by Senior II
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STM32F407 I2C2 busy bit stuck high after configuration

Hi,Saw this (popular) issue on the Q&A and also found many google result regarding this issue, but none of them solve my issue.I'm trying to configured I2C2 bus to work with eeprom.During the configuration, right after setting the I2C RCC clock, the ...

FLast.16 by Associate
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I2C Communication in STM 32 f401 RE

Hi I have omron D6t 32x32 thermal sensor and it give 1023 field of data , How to receive more than 1 byte data in stm? Can any one help me? Also I am storing the value to an character array but i need the value in decimal how to obatin that?

Resolved! Need clarifications on CSS of STM32H7

Hello,I don't understand the description of the Clock Security System in the Ref Manual of STM32H7 (section 7.5.3).First question is : what exactly is the CSS doing ? (what kind of control is done on the clock). What is a definition of "a failure of...

Gpeti by Senior II
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