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At low duty cycle (like below 5%), the timer pwm stops periodically (see the attached picture). The higher the duty cycle, the smaller the stop period. Does anyone know why this happens?For context, I am using the STM32F072 Discovery board. I use Cub...
Scope is configured correctly. Reading of CSR register is done way early in the code and is reliable. Register is cleared after reading. Scope is configured correctly.When we trigger pin reset externally, we can catch it on the scope. When we trigge...
Hi there,I'm trying to implement a multi-master I2C network, where there are several nodes (around 6), any of which can send a message to any other. In other words, all nodes usually acting as slaves, waiting for incoming I2C messages. When any node ...
It is recomanded to set unused pins to analog input.
TIM_HandleTypeDef htim3;DMA_HandleTypeDef hdma_tim3_ch2;/* TIM3 init function */void MX_TIM3_Init(void){ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0}; TIM_OC_InitTypeDef sConfigOC = {0}; htim3.Instance ...
If this device is powered-down (i..e voltage is 0 on all rails), what impedance will be presented by the Port pins? If a pin from a powered-down STM32H743 is connected to a pin on another (fully powered) device, what current drain will occur?
In Section 2.2.13 of ES0392, it states that there is "unexpected leakage current" if Vin >Vdd.What is the bound on the leakage current (assume an FT pin type):Vin = 5V and Vdd = 1.8VVin = 5V and Vdd = 3.3VVin = 3.3V and Vdd = 1.8VThank you.
After causing a watchdog reset RCC->RSR is showing as 0. I didn't think that was a valid value unless a jump was performed. I check RSR first thing so nothing should be clearing the bits by setting RMVF bit. Other types of reset seem to work. I haven...
Hello dear experts,I am using the TIMER2 on stm32F446Re with TI1_ED as reset mode input and TIM2_CH4 as timer value capture input. I inserted code to toggle a gpio in the HAL_TIM_IC_callback. On the scope I am capturating the TIM2_IC4 signal and the ...
