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Trying to integrate the waveplayer from stm32137 example in L4+ MCU. However, the loop updating the DMA buffer only enters DMATxComplete on 3 occasions?

Here's the essence of what I have at the moment. I wonder why it does not enter DMATxComplete, I have tried with 128 and 30 buffer sizes...//****** dac.c **********//   DAC_HandleTypeDef hdac1; DMA_HandleTypeDef hdma_dac_ch1; DMA_HandleTypeDef hdma_d...

VNado.1 by Associate III
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DAC output error

I'm using STM32F405VGT6 to output sine wave by using its dac.After every output sample,which is triggerd by timer, dac's data holding register 'DAC_DHR12R2' is not holding the data and is reset to zero.So the output wave is something like sine wave m...

ZPC.1 by Associate
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wrong data send with slave i2c1 on STM32F103RCT6

STM32F103RCT6 i2c work as slave mode,master i2c machine worked with clock speed 400KHz.When master read many bytes from slave,a wrong data will come out behind the address byte.in normal,master transmits 0xA1,then it will receive 0x11 0x22 0x33 0x44b...

yqiu.11 by Associate
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EXTI line got odd/even interrupts count.

Hi friends,I met a problem.I used one EXTI line to check a button push-and-release. EXTI line was set to be triggered by both falling and raising edge. I know there will be burr when I pushed the bottom. The question is , when I pushed and then relea...

EYang.11 by Associate II
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  • 2 replies
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timer 16 interupt not trigering on a stm32L432

Im migrating the code from a stm32L031 to a stm32L432 and the timer interupt isnt triggering Ive set the LED to toggle in the CaptureCallback. This code works on a L031 using timer22. Clearly Im missing something obvious;void HAL_TIM_IC_CaptureCallba...

PGood.1 by Associate II
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Resolved! Why is SPI clock baud rate limited to 18Mbit/s?

I'm using the STM32F072RB MCU and I am trying to increase the SPI baud rate. The HSI48 Clock is 48MHz and the minimum SPI clock prescaler is 2 which comes out to be 24Mbit/s. However, it gives me an error stating that the baud rate is more than 18MB...

JAlle.2 by Associate II
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