How to achieve exact SCL clock timings for I2C master in transmit mode?
According to RM, "The I2C detects its own SCL low level after a tSYNC1 delay depending on the SCL falling edge", andi2sT=1/i2sclktSCL=tSYNC1+tSYNC2+((SCLH+1)+(SCLL+1))*(PRESC+1)*i2sTfSCL=1/tSCLI tried different PLL clock configurations and altered au...