STM32 MCUs products

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I'm writing the following code: GPIOA-"MODER" 0x400; (set GPIO_MODER_MODE5_0). It's not working! In the debugging window, bit 11 doesn't change and the LD4 LED doesn't switch.

I have Nucleo-G071RB. I want to flash the LED LD4 using CMSIS. Use IAR 8.40I'm writing the following code: GPIOA->MODER |= 0x400; (set GPIO_MODER_MODE5_0). It's not working! In the debugging window, bit 11 doesn't change and the LD4 LED doesn't switc...

VTyut.1 by Associate
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Request for explanations regarding the ICACHE of H5

Using an STM32H5 I recently came across a problem: triggering a hard fault when accessing data in FLASH (read FLASHSIZE_BASE).It turns out in this thread that the ICACHE being validated, it is necessary to configure the MPU to make “uncacheable” the ...

Resolved! CMSIS version for cmsis_device_f3

 It says "It is crucial that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in this release note." but I do not see any CMSIS version in the release notes. Which CMSIS version is recommended for cmsis_device_f3 ?...

mete by Senior
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Resolved! STM32F070RBT Bootloading via USB

According to AN2606 section 12 we can use USB DFU bootloader as long we have HSE using a 24, 18, 16, 12, 8, 6, 4 MHz crystal. This is missing from section 3.3 of the datasheet. Is there a reason for this?

CWedg.1 by Associate II
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Resolved! STM32H562 FLASH Prefetch and ICACHE

Hello,I am currently evaluating the STM32H562 device. This devices has an ICACHE (instruction cache) module.Does it make sense to enable both, the ICACHE module and the FLASH prefetch buffer? In the past I already worked with the G0, G4 and F4 series...

Resolved! STM32G473 extended CAN ID never even

I'm attempting to interface an STM32G473 with a VESC motor controller using CAN.I am successfully receiving status frames from the VESC controller, but when I transmit a frame to command it, the ID my scope reads in the frame is not always the same a...

SRP by Associate II
  • 6 replies
  • 5 kudos

Resolved! Latest STM32L4R9 svd file v2 has removed TIM1_OR1

The new STM32L4R9 svd file (version 2.0) has renamedTIM1_OR2 to TIM1_AF1,TIM1_OR3 to TIM1_AF2Removed TIM1_OR1 which is in the reference manual containing ETR_ADC1_RMP and TI_RMPAdded a new TIM1_TISEL at offset 0x68 which is not in the current referen...

Resolved! De-interleaving DMA output from sequentially configured ADCs

I am using all 3 ADCs on an F765 to convert 16 channels of data at 50 ksps. Each ADC is configured to perform a sequence of conversions (5 on ADC1 and ADC2, 6 on ADC3), all triggered from the same timer. I have also configured them to ping-pong the d...

Nev by Associate II
  • 8 replies
  • 0 kudos