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I have TIM1 configured in one pulse mode triggered by rising edge on TIM1_CH1 to generate single pulse. Timer works correctly (generate single pulse for each rising edge on input). Datasheet claims that TIF flag is set on trigger event in all modes b...
i'm using stm32H7,i want to use ITCM/DTCM ram,so i want add .o file in stm32H7XXXXX.ld filei try .main_section { . = ALIGN(4); CORE/src/main.o(.data); . =ALIGN(4)}>ITCMRAMbut gcc report errorso i want to known how fix it?
OK, I am using STM32H750BV, I have a driver that needs very critical timing control, so I want to use DMA trigger by timer, transfer memory data to GPIO BSRR register, let GPIO can according to time pass to generate the signal, but most of all refe...
I cannot find on st website digital power library for stm32.
Hello everyone,With respect to the Subject I am facing problem in reading analog voltage across the analog pins in the controller specified.Following are the ADC configuration.1. ADC resolution = 12Bit2. Sclk = 256MHz3. ADC clock source = Sclk/44...
Hi,Anyone here successfully connected STM32F103C8T6 clone board using ST-LINK V3SET ?QUESTIONS:1. Here is the pins connection layout using CN2 JTAG:+5V external ----> T_VCC pin 1GND ---------------> GND pin 20SWDIO ------------> T_SWDIO pin 7SWCLK --...
After assembling the X3 external 25MHz crystal and 2 caps and generating initialize code for 550MHz clock with CubeMX my NUCLEO-H723ZG board runs fine, except ADC. It is very noisy. The CubeMX configured the clock for ADC = 96.000671 MHz (PLL2P). In ...
Hello,I have setup a project using the Custom P2P server settings. When I add the HW_time server to it, the code hangs. I have one project in which the code gets into the infinite loop (when debuggin) and I have setup a project with minimalistic use ...
Hi, We have been experiencing severe issues with RX UART on STM32L071.The RX bus stops receiving data while running, and the only way we could recover from it was to initiate the UART back again which probably clears the registers.Is anyone familiar ...
User' manual says that the maximum PLLN or VCO output frequency should be between 100 and 432 MHz (pg. 227). However, I was trying to set the PLL clock and the SysClock to 180 MHz and also respect the 48 MHz clocks.One possible solution is to set the...
