STM32 MCUs Products

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Resolved! STM32F411CEU chip Revision Codes ?

Hi, What are the revisions of the STM32F411CEU6 chip?The ERRATA doc from STM mentions only revision "A" . Are there other revisions?I received board with revision "1" .

eBirdman by Senior II
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Resolved! schematics for microSd on SDMMC

Hello,Do you have schematics suggestion for using a microSD on the SDMMC interface of the STM32L476? The reference manuel only shows data with 8 lines while the microSD has only 4 lines with data3 share with card detect.Do I only need to ignore the c...

MLe M.1 by Associate II
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documentation

hello dear. I opened the documentation for stm32H7xx and am trying to calculate the address. I don't understand what it means?Address offset: 0x3DCh-0x3EChwhat should I add to the base address?0x40017400how to understand and read it?Address offset: 0...

MTS by Associate II
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I2C blocking function fails to output the expected outputs

I'm currently trying to learn about how the HAL blocking functions of I2C works on the STM32H7B3I-DK. However, the master device fails to receive any data unless HAL_I2C_Master_Transmit() is called before it.For example, the following code doesn't pr...

JTurn.2 by Senior
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Learning Materials for Beginners

Hello.Is there a complete course or book from start to finish for beginners on new ST programs? I want to switch from arduino.I found the book Carmine Noviello Mastering STM32, but it is old (2017-2018) and it uses an eclipse. I want to find a full-f...

Pavel1 by Associate II
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  • 11 replies
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SPI MOSI idle state quirk - sometimes high, sometimes low

I'm DMAing a buffer to the SPI transmitter, and require the idle state of the MOSI line to be low while the next buffer is waiting for its queue to be sent. After some limited testing (STM32L433) I have found that the idle state of the line depends o...

gregstm by Senior III
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