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Resolved! AN4661 interface signal layout guidelines for high speed SDMMC operation states "keep the same number of via between data signals". Am I interpreting this correctly?

I am interpreting this to mean that each data signal (including CMD line) should all contain equal number of vias. For example if line D0 is routed to MCU and this trace requires 2 vias on its path to the MCU then all other data signals should also c...

RMora.4 by Associate III
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Resolved! Clock recovery system CRS

Hello,I have problem with CRS (Clock recovery system) in STM32F091xx. I use HSI48 and I want to generate synchronization with LSE (32.768 kHz).How to set FELIM in CFGR register and TRIM in CR register ?Thank your for help.

pferd by Associate III
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PWM capture with TIMER (with DMA)

I have configured TIMER2 to capture PWM input (Basically PWM inputmode). Both CCR1 and CCR2 captures period and ontime of the PWM signal respectively. I configured DMA to captures these two registers CCR1 and CCR2 by configuring array of two 32bit bu...

Shakthi by Associate II
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RTC Initialization have a problem.

HiI created my new project follow SubGHz Phy Ping Pong example project. This is my MX_RTC_Init() function:void MX_RTC_Init(void) {   /* USER CODE BEGIN RTC_Init 0 */   /* USER CODE END RTC_Init 0 */   RTC_TimeTypeDef sTime = {0}; RTC_DateType...

Setting timer 1 channel 4 high on startup

I am using Timer 1 DMA to generate a waveform. The generation part works fine, but the waveform is inverted, so I need to set channel 4 (output of CC4) signal high during initialization. I have tried a bunch of thing, my latest attempt is below. W...

JMala.3 by Associate III
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  • 8 replies
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