Resolved! AN4661 interface signal layout guidelines for high speed SDMMC operation states "keep the same number of via between data signals". Am I interpreting this correctly?
I am interpreting this to mean that each data signal (including CMD line) should all contain equal number of vias. For example if line D0 is routed to MCU and this trace requires 2 vias on its path to the MCU then all other data signals should also c...