Hello,I'm working on a small scale project. In my earlier design, I've used the STM32F100x series. Now as the STM introduced a new set of controllers, the STM32G series ( which is less in cost and much higher efficiency than STM32F series), I've migr...
I have been using printf() to output to UART for many years on a STM32L052All these projects still compile and printf() to UART, no problem.I started a NEW project with CubeMX, but now printf() does NOT print to UART.I use the same int fputc(int ch, ...
I am not much of a software/firmware developer, but i need to get a basic Driver working for NAND flash device "MT29F128G08AJAAAWP-ITZ" working on a "NUCLEO-L496ZG".I have the device wired up to the eval board, and need to build a basic drive to writ...
Hi, I am currently working on a display driver board, with a STM32F767. And I would like to use the FMC with a SDRAM.My problem is that the MCU is clocked at 216MHz, the SDRAM max clock is 133MHz, on the F767 documentation, it is written that the max...
Currently we are using Nucleo F746ZG controller with 216 MHZ frequency.We are able to get high toggle frequency on GPIO with this board.Now we want to shift to Micro Processor for parallel processing.So is there any Better Controller/Processor availa...
Hello!I'm working this UART+DMA with idle detection and ring buffer. My STM32F4707VET6 receives data from a sensor and then sends it by USB, the data received by USB should look like this:$1651500,-5,-228,-988,-3,-217,-976,-102$1651510,-4,-228,-987,-...
I am using the STM32F746VET6 with a project generated using MX v6.5.0.I am using interfacing to several I2C chips in my project and they are operation correctly. When I started checking the return values from the HAL_I2C_Master_Receive() function, ho...
HiI have made a board using the g051k6 chip. I have not been able to receive data from another board sending data at 115200 bd. I connected another serial port to the input pin , and all data is received without errors. A uart problem is mentioned...
SRAM parity check is enabled. In fact, breakpoint in NMI is reached.But SYSCFG_CFGR2.SRAM_PEF bit is NOT set. See .png.Disassembly (at bottom) shows, that address of CFGR2 is loaded at R0 ("Registers" to the right) and its contents is loaded to R1. T...
